[llvm] [RISCV] Optimize pattern `(setcc (selectLT (vfirst_vl ...) , 0, EVL, ...), EVL)` (PR #90538)

[Min-Yih Hsu via llvm-commits]

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@@ -13678,9 +13687,88 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
   EVT VT = N->getValueType(0);
   EVT OpVT = N0.getValueType();
+  SDLoc DL(N);
+
+  // Both rules are looking for an equality compare.
+  if (!isIntEqualitySetCC(Cond))
+    return SDValue();
+
+  // Rule 1
+  using namespace SDPatternMatch;
+  auto matchSelectCC = [](SDValue Op, SDValue VLCandidate, bool Inverse,
+                          SDValue &Select) -> bool {
+    // Remove any sext or zext
+    auto ExtPattern =
+        m_AnyOf(m_Opc(ISD::SIGN_EXTEND_INREG), m_And(m_Value(), m_AllOnes()));
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mshockwave wrote:

It's fixed now. In this particular case I think VL will almost certain be zext from i32 so I'm pattern matching `(and X, <32 trailing ones>)` here instead.

https://github.com/llvm/llvm-project/pull/90538