[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

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@@ -1502,14 +1668,14 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
   // we need to prove the value is available at the point we're going
   // to insert the vsetvli at.
   if (AvailableInfo.hasAVLReg()) {
-    const MachineInstr *AVLDefMI = &AvailableInfo.getAVLDefMI();
+    SlotIndex SI = AvailableInfo.getAVLVNInfo()->def;
     // This is an inline dominance check which covers the case of
     // UnavailablePred being the preheader of a loop.
-    if (AVLDefMI->getParent() != UnavailablePred)
+    if (LIS->getMBBFromIndex(SI) != UnavailablePred)
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lukel97 wrote:

> By the way riscv-vsetvli-after-rvv-regalloc=false situation, pass manager will invoke LiveIntervals and prepare LIS before into vsetvli pass. it is due to AU.addRequired<LiveIntervals>();

Ah that makes sense, sorry for the confusion. So to double check my understanding, we'll always have LiveIntervals but we may or not be in SSA depending on `riscv-vsetvli-after-rvv-regalloc`?

https://github.com/llvm/llvm-project/pull/70549