[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

BeMg wrote:

Here is the lit test that generate the extra vsetvli or spill/reload code

```
SPILL inc, RELOAD inc, VSETVL inc, TEST name	
14	30	-32	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll--check-prefixes=CHECKRV32
14	30	-32	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll--check-prefixes=CHECKRV32
0	0	10	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll--check-prefixes=CHECKRV32
0	0	8	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll-check-prefixes=CHECKRV32
4	4	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
2	5	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll--check-prefixes=CHECKZVFH
2	5	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll--check-prefixes=CHECKZVFH
2	2	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
2	3	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll--check-prefixes=CHECKZVFHMIN
0	0	4	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll--check-prefixes=CHECKRV32
0	0	4	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll-check-prefix=ZVE32X
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll--check-prefixes=CHECKRV32
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll--check-prefixes=CHECKRV32
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll--check-prefixes=CHECKRV32
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll--check-prefixes=CHECKZVFHMIN
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll--check-prefixes=CHECKZVFHMIN
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll--check-prefixes=CHECKRV32
2	2	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/compressstore.ll--check-prefix=RV64
0	0	3	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll--check-prefixes=CHECKRV32
0	0	2	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll--check-prefixes=CHECKRV32
0	0	2	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll--check-prefixes=CHECKRV32
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll--check-prefixes=CHECKZVFHMIN
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll--check-prefixes=CHECKZVFHMIN
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll--check-prefixes=CHECKZVFHMIN
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll--check-prefixes=CHECKZVFHMIN
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll--check-prefixes=CHECKZVFH
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll--check-prefixes=CHECKZVFH
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll--check-prefixes=CHECKZVFH
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll--check-prefixes=CHECKZVFH
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
1	1	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
1	2	-1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll--check-prefixes=CHECKRV32RV32V
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll--check-prefixes=CHECKVLARV32VLA
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll--check-prefixes=CHECKRV32
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
0	0	1	llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
1	0	0	llvm-project/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll--check-prefixes=CHECKRV32
1	1	-1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll--check-prefixes=CHECKZVFH
1	1	-1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll--check-prefixes=CHECKZVFH
1	1	-1	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
-1	-1	2	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
7	13	-22	llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll--check-prefixes=CHECKRV32
```

https://github.com/llvm/llvm-project/pull/70549