[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -51,6 +51,38 @@ static cl::opt<bool> UseStrictAsserts(
 
 namespace {
 
+// For the SSA form, we could just use the getVRegDef to take Reaching
+// definition. For the non-SSA, we retrieve reaching definition for specific
+// register from LiveInterval/VNInfo.
+template <typename T>
+static T *getReachingDefMI(Register Reg, T *MI, const MachineRegisterInfo *MRI,
+                           const LiveIntervals *LIS) {
+  
+  if (MRI->isSSA() || !MI)
+    return MRI->getUniqueVRegDef(Reg);
+
+  // For O0 situation
+  if (!LIS)
+    return nullptr;
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BeMg wrote:

Agree. Enabling it by default will uncover more potential issue/improvement. 




https://github.com/llvm/llvm-project/pull/70549