[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -567,10 +606,13 @@ class VSETVLIInfo {
   }
 
   bool hasSameAVL(const VSETVLIInfo &Other) const {
-    if (hasAVLReg() && Other.hasAVLReg())
+    if (hasAVLRegDefMI() && Other.hasAVLRegDefMI())
       return getAVLDefMI().isIdenticalTo(Other.getAVLDefMI()) &&
              getAVLReg() == Other.getAVLReg();
 
+    if (hasAVLReg() && Other.hasAVLReg())
+      return getAVLReg() == Other.getAVLReg();
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BeMg wrote:

I'm cherry-pick the https://github.com/lukel97/llvm-project/commit/47a6d183fbe81178dac668eda1a6f50d184a0dba with slight change. 

Using the VNInfo to represent the Def of AVL is  good idea. Thanks!

https://github.com/llvm/llvm-project/pull/70549