[llvm] [RISCV] Move RISCVDeadRegisterDefinitions to post regalloc (PR #90636)

[Luke Lau via llvm-commits]

lukel97 wrote:

> If all the non-reserved registers are in use, the register allocation won't pick X0. It would spill to pick a non-reserved register.

That makes more sense, I forgot that X0 was reserved.

@BeMg I also found we have some regressions in #70549 since this no longer runs after vsetvli insertion, it seems to affect cases where two vsetvlis were coalesced e.g.:

```diff
 define <vscale x 1 x double> @test1(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli a0, a0, e64, m1, ta, ma
 ; CHECK-NEXT:    vfadd.vv v8, v8, v9
 ; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
  %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
    <vscale x 1 x double> undef,
    <vscale x 1 x double> %a,
    <vscale x 1 x double> %b,
    i64 7, i64 %0)
  ret <vscale x 1 x double> %1
}
```

We could potentially run this twice, before regalloc and after regalloc. Or I think we might be able to also make coalescing smarter and have it preserve the x0 def.

https://github.com/llvm/llvm-project/pull/90636