[llvm] [RISCV] Move RISCVDeadRegisterDefinitions to post regalloc (PR #90636)

[Craig Topper via llvm-commits]

topperc wrote:

Other than vsetvli, the original patch only affected atomics and non-volatile loads. I'm not sure if those are well tested by SPEC or llvm-test-suite. Especially in high register pressure situation.

> believe the register allocator already accounts for dead defs hence why this almost an NFC.

If all the non-reserved registers are in use, the register allocation won't pick X0. It would spill to pick a non-reserved register.

https://github.com/llvm/llvm-project/pull/90636