[llvm] 91c52b9 - [DAG] Pull out repeated SDLoc() from SHL/SRL/SRA combines. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 30 09:31:12 PDT 2024
Author: Simon Pilgrim
Date: 2024-04-30T17:30:43+01:00
New Revision: 91c52b966a09e37a96ed87bcf5b422de7711bf50
URL: https://github.com/llvm/llvm-project/commit/91c52b966a09e37a96ed87bcf5b422de7711bf50
DIFF: https://github.com/llvm/llvm-project/commit/91c52b966a09e37a96ed87bcf5b422de7711bf50.diff
LOG: [DAG] Pull out repeated SDLoc() from SHL/SRL/SRA combines. NFC.
We were always calling SDLoc(N) at the top of each visitSHL/SRL/SRA for the FoldConstantArithmetic call, so just reuse this as much as possible.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3fa8a3578b4fb4..c0bbea16a64262 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9740,17 +9740,18 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (SDValue V = DAG.simplifyShift(N0, N1))
return V;
+ SDLoc DL(N);
EVT VT = N0.getValueType();
EVT ShiftVT = N1.getValueType();
unsigned OpSizeInBits = VT.getScalarSizeInBits();
// fold (shl c1, c2) -> c1<<c2
- if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, {N0, N1}))
+ if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, DL, VT, {N0, N1}))
return C;
// fold vector ops
if (VT.isVector()) {
- if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N)))
+ if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))
return FoldedVOp;
BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
@@ -9766,8 +9767,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
TargetLowering::ZeroOrNegativeOneBooleanContent) {
if (SDValue C =
- DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, {N01, N1}))
- return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
+ DAG.FoldConstantArithmetic(ISD::SHL, DL, VT, {N01, N1}))
+ return DAG.getNode(ISD::AND, DL, VT, N00, C);
}
}
}
@@ -9778,13 +9779,13 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// if (shl x, c) is known to be zero, return 0
if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits)))
- return DAG.getConstant(0, SDLoc(N), VT);
+ return DAG.getConstant(0, DL, VT);
// fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND) {
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
- return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
+ return DAG.getNode(ISD::SHL, DL, VT, N0, NewOp1);
}
// fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
@@ -9797,7 +9798,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
return (c1 + c2).uge(OpSizeInBits);
};
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
- return DAG.getConstant(0, SDLoc(N), VT);
+ return DAG.getConstant(0, DL, VT);
auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS,
ConstantSDNode *RHS) {
@@ -9807,7 +9808,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
return (c1 + c2).ult(OpSizeInBits);
};
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
- SDLoc DL(N);
SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum);
}
@@ -9838,7 +9838,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchOutOfRange,
/*AllowUndefs*/ false,
/*AllowTypeMismatch*/ true))
- return DAG.getConstant(0, SDLoc(N), VT);
+ return DAG.getConstant(0, DL, VT);
auto MatchInRange = [OpSizeInBits, InnerBitwidth](ConstantSDNode *LHS,
ConstantSDNode *RHS) {
@@ -9851,7 +9851,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchInRange,
/*AllowUndefs*/ false,
/*AllowTypeMismatch*/ true)) {
- SDLoc DL(N);
SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0));
SDValue Sum = DAG.getZExtOrTrunc(InnerShiftAmt, DL, ShiftVT);
Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, Sum, N1);
@@ -9876,7 +9875,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchEqual,
/*AllowUndefs*/ false,
/*AllowTypeMismatch*/ true)) {
- SDLoc DL(N);
EVT InnerShiftAmtVT = N0Op0.getOperand(1).getValueType();
SDValue NewSHL = DAG.getZExtOrTrunc(N1, DL, InnerShiftAmtVT);
NewSHL = DAG.getNode(ISD::SHL, DL, N0Op0.getValueType(), N0Op0, NewSHL);
@@ -9893,9 +9891,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
return LHSC.ult(OpSizeInBits) && RHSC.ult(OpSizeInBits) &&
LHSC.getZExtValue() <= RHSC.getZExtValue();
};
-
- SDLoc DL(N);
-
+
// fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
// fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 >= C2
if (N0->getFlags().hasExact()) {
@@ -9949,7 +9945,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
isConstantOrConstantVector(N1, /* No Opaques */ true)) {
- SDLoc DL(N);
SDValue AllBits = DAG.getAllOnesConstant(DL, VT);
SDValue HiBitsMask = DAG.getNode(ISD::SHL, DL, VT, AllBits, N1);
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask);
@@ -9970,7 +9965,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// Preserve the disjoint flag for Or.
if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
Flags.setDisjoint(true);
- return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1, Flags);
+ return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
}
}
@@ -10000,7 +9995,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
SDValue N01 = N0.getOperand(1);
if (SDValue Shl =
DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, {N01, N1}))
- return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl);
+ return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), Shl);
}
ConstantSDNode *N1C = isConstOrConstSplat(N1);
@@ -10015,7 +10010,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (N0.getOpcode() == ISD::VSCALE && N1C) {
const APInt &C0 = N0.getConstantOperandAPInt(0);
const APInt &C1 = N1C->getAPIntValue();
- return DAG.getVScale(SDLoc(N), VT, C0 << C1);
+ return DAG.getVScale(DL, VT, C0 << C1);
}
// Fold (shl step_vector(C0), C1) to (step_vector(C0 << C1)).
@@ -10025,7 +10020,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
const APInt &C0 = N0.getConstantOperandAPInt(0);
if (ShlVal.ult(C0.getBitWidth())) {
APInt NewStep = C0 << ShlVal;
- return DAG.getStepVector(SDLoc(N), VT, NewStep);
+ return DAG.getStepVector(DL, VT, NewStep);
}
}
@@ -10036,7 +10031,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// Examples:
// (srl (mul (zext i32:$a to i64), (zext i32:$a to i64)), 32) -> (mulhu $a, $b)
// (sra (mul (sext i32:$a to i64), (sext i32:$a to i64)), 32) -> (mulhs $a, $b)
-static SDValue combineShiftToMULH(SDNode *N, SelectionDAG &DAG,
+static SDValue combineShiftToMULH(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
const TargetLowering &TLI) {
assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
"SRL or SRA node is required here!");
@@ -10047,8 +10042,6 @@ static SDValue combineShiftToMULH(SDNode *N, SelectionDAG &DAG,
if (!ShiftAmtSrc)
return SDValue();
- SDLoc DL(N);
-
// The operation feeding into the shift must be a multiply.
SDValue ShiftOperand = N->getOperand(0);
if (ShiftOperand.getOpcode() != ISD::MUL)
@@ -10190,11 +10183,12 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
if (SDValue V = DAG.simplifyShift(N0, N1))
return V;
+ SDLoc DL(N);
EVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getScalarSizeInBits();
// fold (sra c1, c2) -> (sra c1, c2)
- if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, {N0, N1}))
+ if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, DL, VT, {N0, N1}))
return C;
// Arithmetic shifting an all-sign-bit value is a no-op.
@@ -10205,7 +10199,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// fold vector ops
if (VT.isVector())
- if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N)))
+ if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))
return FoldedVOp;
if (SDValue NewSel = foldBinOpIntoSelect(N))
@@ -10216,7 +10210,6 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
// clamp (add c1, c2) to max shift.
if (N0.getOpcode() == ISD::SRA) {
- SDLoc DL(N);
EVT ShiftVT = N1.getValueType();
EVT ShiftSVT = ShiftVT.getScalarType();
SmallVector<SDValue, 16> ShiftValues;
@@ -10273,7 +10266,6 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
TLI.isTruncateFree(VT, TruncVT)) {
- SDLoc DL(N);
SDValue Amt = DAG.getConstant(ShiftAmt, DL,
getShiftAmountTy(N0.getOperand(0).getValueType()));
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
@@ -10314,7 +10306,6 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// that restriction may conflict with other transforms.
if (TruncVT.isSimple() && isTypeLegal(TruncVT) &&
TLI.isTruncateFree(VT, TruncVT)) {
- SDLoc DL(N);
SDValue Trunc = DAG.getZExtOrTrunc(Shl.getOperand(0), DL, TruncVT);
SDValue ShiftC =
DAG.getConstant(AddC->getAPIntValue().lshr(ShiftAmt).trunc(
@@ -10335,7 +10326,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND) {
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
- return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
+ return DAG.getNode(ISD::SRA, DL, VT, N0, NewOp1);
}
// fold (sra (trunc (sra x, c1)), c2) -> (trunc (sra x, c1 + c2))
@@ -10352,7 +10343,6 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
EVT LargeVT = N0Op0.getValueType();
unsigned TruncBits = LargeVT.getScalarSizeInBits() - OpSizeInBits;
if (LargeShift->getAPIntValue() == TruncBits) {
- SDLoc DL(N);
EVT LargeShiftVT = getShiftAmountTy(LargeVT);
SDValue Amt = DAG.getZExtOrTrunc(N1, DL, LargeShiftVT);
Amt = DAG.getNode(ISD::ADD, DL, LargeShiftVT, Amt,
@@ -10370,7 +10360,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// If the sign bit is known to be zero, switch this to a SRL.
if (DAG.SignBitIsZero(N0))
- return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
+ return DAG.getNode(ISD::SRL, DL, VT, N0, N1);
if (N1C && !N1C->isOpaque())
if (SDValue NewSRA = visitShiftByConstant(N))
@@ -10378,7 +10368,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// Try to transform this shift into a multiply-high if
// it matches the appropriate pattern detected in combineShiftToMULH.
- if (SDValue MULH = combineShiftToMULH(N, DAG, TLI))
+ if (SDValue MULH = combineShiftToMULH(N, DL, DAG, TLI))
return MULH;
// Attempt to convert a sra of a load into a narrower sign-extending load.
@@ -10394,17 +10384,18 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (SDValue V = DAG.simplifyShift(N0, N1))
return V;
+ SDLoc DL(N);
EVT VT = N0.getValueType();
EVT ShiftVT = N1.getValueType();
unsigned OpSizeInBits = VT.getScalarSizeInBits();
// fold (srl c1, c2) -> c1 >>u c2
- if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, {N0, N1}))
+ if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, DL, VT, {N0, N1}))
return C;
// fold vector ops
if (VT.isVector())
- if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N)))
+ if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))
return FoldedVOp;
if (SDValue NewSel = foldBinOpIntoSelect(N))
@@ -10414,7 +10405,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (N1C &&
DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits)))
- return DAG.getConstant(0, SDLoc(N), VT);
+ return DAG.getConstant(0, DL, VT);
// fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
if (N0.getOpcode() == ISD::SRL) {
@@ -10426,7 +10417,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
return (c1 + c2).uge(OpSizeInBits);
};
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
- return DAG.getConstant(0, SDLoc(N), VT);
+ return DAG.getConstant(0, DL, VT);
auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS,
ConstantSDNode *RHS) {
@@ -10436,7 +10427,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
return (c1 + c2).ult(OpSizeInBits);
};
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
- SDLoc DL(N);
SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum);
}
@@ -10455,7 +10445,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// srl (trunc (srl x, c1)), c2 --> 0 or (trunc (srl x, (add c1, c2)))
// This is only valid if the OpSizeInBits + c1 = size of inner shift.
if (c1 + OpSizeInBits == InnerShiftSize) {
- SDLoc DL(N);
if (c1 + c2 >= InnerShiftSize)
return DAG.getConstant(0, DL, VT);
SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT);
@@ -10467,7 +10456,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// srl (trunc (srl x, c1)), c2 --> trunc (and (srl x, (c1+c2)), Mask)
if (N0.hasOneUse() && InnerShift.hasOneUse() &&
c1 + c2 < InnerShiftSize) {
- SDLoc DL(N);
SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT);
SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
InnerShift.getOperand(0), NewShiftAmt);
@@ -10495,7 +10483,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
/*AllowUndefs*/ false,
/*AllowTypeMismatch*/ true)) {
- SDLoc DL(N);
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1);
SDValue Mask = DAG.getAllOnesConstant(DL, VT);
@@ -10507,7 +10494,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
/*AllowUndefs*/ false,
/*AllowTypeMismatch*/ true)) {
- SDLoc DL(N);
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01);
SDValue Mask = DAG.getAllOnesConstant(DL, VT);
@@ -10535,7 +10521,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
getShiftAmountTy(SmallVT)));
AddToWorklist(SmallShift.getNode());
APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt);
- SDLoc DL(N);
return DAG.getNode(ISD::AND, DL, VT,
DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift),
DAG.getConstant(Mask, DL, VT));
@@ -10546,7 +10531,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// bit, which is unmodified by sra.
if (N1C && N1C->getAPIntValue() == (OpSizeInBits - 1)) {
if (N0.getOpcode() == ISD::SRA)
- return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
+ return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
}
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit), and x has a power
@@ -10581,10 +10566,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
getShiftAmountTy(Op.getValueType())));
AddToWorklist(Op.getNode());
}
-
- SDLoc DL(N);
- return DAG.getNode(ISD::XOR, DL, VT,
- Op, DAG.getConstant(1, DL, VT));
+ return DAG.getNode(ISD::XOR, DL, VT, Op, DAG.getConstant(1, DL, VT));
}
}
@@ -10592,7 +10574,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND) {
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
- return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
+ return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
}
// fold operands of srl based on knowledge that the low bits are not
@@ -10646,7 +10628,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// Try to transform this shift into a multiply-high if
// it matches the appropriate pattern detected in combineShiftToMULH.
- if (SDValue MULH = combineShiftToMULH(N, DAG, TLI))
+ if (SDValue MULH = combineShiftToMULH(N, DL, DAG, TLI))
return MULH;
return SDValue();
@@ -10772,11 +10754,11 @@ SDValue DAGCombiner::visitSHLSAT(SDNode *N) {
if (SDValue V = DAG.simplifyShift(N0, N1))
return V;
+ SDLoc DL(N);
EVT VT = N0.getValueType();
// fold (*shlsat c1, c2) -> c1<<c2
- if (SDValue C =
- DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1}))
+ if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
return C;
ConstantSDNode *N1C = isConstOrConstSplat(N1);
@@ -10785,13 +10767,13 @@ SDValue DAGCombiner::visitSHLSAT(SDNode *N) {
// fold (sshlsat x, c) -> (shl x, c)
if (N->getOpcode() == ISD::SSHLSAT && N1C &&
N1C->getAPIntValue().ult(DAG.ComputeNumSignBits(N0)))
- return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1);
+ return DAG.getNode(ISD::SHL, DL, VT, N0, N1);
// fold (ushlsat x, c) -> (shl x, c)
if (N->getOpcode() == ISD::USHLSAT && N1C &&
N1C->getAPIntValue().ule(
DAG.computeKnownBits(N0).countMinLeadingZeros()))
- return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1);
+ return DAG.getNode(ISD::SHL, DL, VT, N0, N1);
}
return SDValue();
@@ -11185,7 +11167,8 @@ SDValue DAGCombiner::combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
/// If a (v)select has a condition value that is a sign-bit test, try to smear
/// the condition operand sign-bit across the value width and use it as a mask.
-static SDValue foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) {
+static SDValue foldSelectOfConstantsUsingSra(SDNode *N, const SDLoc &DL,
+ SelectionDAG &DAG) {
SDValue Cond = N->getOperand(0);
SDValue C1 = N->getOperand(1);
SDValue C2 = N->getOperand(2);
@@ -11205,14 +11188,12 @@ static SDValue foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) {
if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(CondC) &&
isAllOnesOrAllOnesSplat(C2)) {
// i32 X > -1 ? C1 : -1 --> (X >>s 31) | C1
- SDLoc DL(N);
SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT);
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
return DAG.getNode(ISD::OR, DL, VT, Sra, C1);
}
if (CC == ISD::SETLT && isNullOrNullSplat(CondC) && isNullOrNullSplat(C2)) {
// i8 X < 0 ? C1 : 0 --> (X >>s 7) & C1
- SDLoc DL(N);
SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT);
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
return DAG.getNode(ISD::AND, DL, VT, Sra, C1);
@@ -11352,7 +11333,7 @@ SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
return DAG.getNode(ISD::OR, DL, VT, NotCond, N1);
}
- if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG))
+ if (SDValue V = foldSelectOfConstantsUsingSra(N, DL, DAG))
return V;
return SDValue();
@@ -12073,7 +12054,7 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
return DAG.getNode(ISD::SHL, DL, VT, ZextCond, ShAmtC);
}
- if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG))
+ if (SDValue V = foldSelectOfConstantsUsingSra(N, DL, DAG))
return V;
// The general case for select-of-constants:
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