[llvm] [InstCombine] Transform high latency, dependent FSQRT/FDIV into FMUL (PR #87474)

[Joshua Cranmer via llvm-commits]

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@@ -626,6 +626,100 @@ Instruction *InstCombinerImpl::foldPowiReassoc(BinaryOperator &I) {
   return nullptr;
 }
 
+static bool isFSqrtDivToFMulLegal(Instruction *X,
+                                  const SmallVectorImpl<Instruction *> &R1,
+                                  const SmallVectorImpl<Instruction *> &R2) {
+  BasicBlock *BBx = X->getParent();
+  BasicBlock *BBr1 = R1[0]->getParent();
+  BasicBlock *BBr2 = R2[0]->getParent();
+  // Check the constaints on instruction X.
+  auto XConstraintsSatisfied = [X]() {
+    // We change x = 1/sqrt(a) to x = sqrt(a) * 1/a . This change isn't allowed
+    // by recip fp as it is strictly meant to transform ops of type a/b to
+    // a * 1/b. So, this can be considered as algebraic rewrite and reassoc flag
+    // has been used(rather abused)in the past for algebraic rewrites.
+    return X->hasAllowReassoc();
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jcranmer-intel wrote:

You also need the `sqrt` to have the `reassoc` flag--every instruction in a reassociated expression needs `reassoc`, not just one of them.

https://github.com/llvm/llvm-project/pull/87474