[llvm] [AArch64][GlobalISel] Select G_ICMP Zero Instruction (PR #90054)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 29 08:34:52 PDT 2024
https://github.com/chuongg3 updated https://github.com/llvm/llvm-project/pull/90054
>From df6070e456acad27a2d02c64e107c33370a96121 Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Wed, 24 Apr 2024 09:46:10 +0000
Subject: [PATCH 1/4] [AArch64][GlobalISel] Pre-commit Test for Select G_ICMP
instruction through TableGen
---
llvm/test/CodeGen/AArch64/icmp.ll | 941 ++++++++++++++++++++++++++----
1 file changed, 839 insertions(+), 102 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 8e10847e7aae34..4e2c62fbd4539a 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -52,16 +52,847 @@ entry:
ret i8 %s
}
-define <2 x i64> @v2i64_i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %d, <2 x i64> %e) {
-; CHECK-LABEL: v2i64_i64:
-; CHECK: // %bb.0: // %entry
+define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp eq <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp eq <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %cmp = icmp eq <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-SD-LABEL: test_v2i16_eq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_v2i16_eq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %cmp = icmp eq <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp eq <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %cmp = icmp eq <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %cmp = icmp eq <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %cmp = icmp eq <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_ne(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: mvn v0.16b, v0.16b
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp ne <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_ne(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: mvn v0.16b, v0.16b
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp ne <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_ne(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mvn v0.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp ne <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_ne(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-SD-LABEL: test_v2i16_ne:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: mvn v0.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_v2i16_ne:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: mvn v0.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %cmp = icmp ne <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_ne(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: mvn v0.16b, v0.16b
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp ne <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_ne(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: mvn v0.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp ne <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_ne(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: mvn v0.16b, v0.16b
+; CHECK-NEXT: ret
+ %cmp = icmp ne <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_ne(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_ne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: mvn v0.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp ne <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-SD-LABEL: test_v2i16_ugt:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-SD-NEXT: cmhi v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_v2i16_ugt:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: cmhi v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %cmp = icmp ugt <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %cmp = icmp ugt <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp uge <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp uge <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %cmp = icmp uge <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-SD-LABEL: test_v2i16_uge:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-SD-NEXT: cmhs v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_v2i16_uge:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: cmhs v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %cmp = icmp uge <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp uge <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %cmp = icmp uge <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %cmp = icmp uge <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %cmp = icmp uge <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp ult <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp ult <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp ult <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-LABEL: test_v2i16_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp ult <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp ult <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+ %cmp = icmp ult <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %cmp = icmp ult <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp ult <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp ule <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp ule <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp ule <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-LABEL: test_v2i16_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp ule <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp ule <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+ %cmp = icmp ule <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %cmp = icmp ule <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp ule <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-SD-LABEL: test_v2i16_sgt:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16
+; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #16
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_v2i16_sgt:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-GI-NEXT: shl v1.2s, v1.2s, #16
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #16
+; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %cmp = icmp sgt <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %cmp = icmp sgt <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp sge <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp sge <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %cmp = icmp sge <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-SD-LABEL: test_v2i16_sge:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16
+; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #16
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-SD-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_v2i16_sge:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-GI-NEXT: shl v1.2s, v1.2s, #16
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #16
+; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %cmp = icmp sge <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp sge <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %cmp = icmp sge <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %cmp = icmp sge <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %cmp = icmp sge <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_slt:
+; CHECK: // %bb.0:
; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
-entry:
- %c = icmp slt <2 x i64> %a, %b
- %s = select <2 x i1> %c, <2 x i64> %d, <2 x i64> %e
- ret <2 x i64> %s
+ %cmp = icmp slt <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp slt <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp slt <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-LABEL: test_v2i16_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-NEXT: shl v1.2s, v1.2s, #16
+; CHECK-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-NEXT: sshr v1.2s, v1.2s, #16
+; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp slt <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp slt <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+ %cmp = icmp slt <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %cmp = icmp slt <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp slt <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) {
+; CHECK-LABEL: test_v2i64_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %cmp = icmp sle <2 x i64> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: test_v4i32_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %cmp = icmp sle <4 x i32> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) {
+; CHECK-LABEL: test_v2i32_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp sle <2 x i32> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) {
+; CHECK-LABEL: test_v2i16_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-NEXT: shl v1.2s, v1.2s, #16
+; CHECK-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-NEXT: sshr v1.2s, v1.2s, #16
+; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %cmp = icmp sle <2 x i16> %v1, %v2
+ ret <2 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: test_v8i16_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
+ %cmp = icmp sle <8 x i16> %v1, %v2
+ ret <8 x i1> %cmp
+}
+
+define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) {
+; CHECK-LABEL: test_v4i16_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+ %cmp = icmp sle <4 x i16> %v1, %v2
+ ret <4 x i1> %cmp
+}
+
+define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: test_v16i8_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %cmp = icmp sle <16 x i8> %v1, %v2
+ ret <16 x i1> %cmp
+}
+
+define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) {
+; CHECK-LABEL: test_v8i8_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %cmp = icmp sle <8 x i8> %v1, %v2
+ ret <8 x i1> %cmp
}
define <3 x i64> @v3i64_i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %d, <3 x i64> %e) {
@@ -128,40 +959,6 @@ entry:
ret <3 x i64> %s
}
-define <4 x i64> @v4i64_i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %d, <4 x i64> %e) {
-; CHECK-SD-LABEL: v4i64_i64:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d
-; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d
-; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b
-; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: v4i64_i64:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d
-; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d
-; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b
-; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b
-; CHECK-GI-NEXT: ret
-entry:
- %c = icmp slt <4 x i64> %a, %b
- %s = select <4 x i1> %c, <4 x i64> %d, <4 x i64> %e
- ret <4 x i64> %s
-}
-
-define <2 x i32> @v2i32_i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %d, <2 x i32> %e) {
-; CHECK-LABEL: v2i32_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
-; CHECK-NEXT: ret
-entry:
- %c = icmp slt <2 x i32> %a, %b
- %s = select <2 x i1> %c, <2 x i32> %d, <2 x i32> %e
- ret <2 x i32> %s
-}
-
define <3 x i32> @v3i32_i32(<3 x i32> %a, <3 x i32> %b, <3 x i32> %d, <3 x i32> %e) {
; CHECK-SD-LABEL: v3i32_i32:
; CHECK-SD: // %bb.0: // %entry
@@ -194,18 +991,6 @@ entry:
ret <3 x i32> %s
}
-define <4 x i32> @v4i32_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %d, <4 x i32> %e) {
-; CHECK-LABEL: v4i32_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: ret
-entry:
- %c = icmp slt <4 x i32> %a, %b
- %s = select <4 x i1> %c, <4 x i32> %d, <4 x i32> %e
- ret <4 x i32> %s
-}
-
define <8 x i32> @v8i32_i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %d, <8 x i32> %e) {
; CHECK-SD-LABEL: v8i32_i32:
; CHECK-SD: // %bb.0: // %entry
@@ -228,30 +1013,6 @@ entry:
ret <8 x i32> %s
}
-define <4 x i16> @v4i16_i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %d, <4 x i16> %e) {
-; CHECK-LABEL: v4i16_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
-; CHECK-NEXT: ret
-entry:
- %c = icmp slt <4 x i16> %a, %b
- %s = select <4 x i1> %c, <4 x i16> %d, <4 x i16> %e
- ret <4 x i16> %s
-}
-
-define <8 x i16> @v8i16_i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %d, <8 x i16> %e) {
-; CHECK-LABEL: v8i16_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: ret
-entry:
- %c = icmp slt <8 x i16> %a, %b
- %s = select <8 x i1> %c, <8 x i16> %d, <8 x i16> %e
- ret <8 x i16> %s
-}
-
define <16 x i16> @v16i16_i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %d, <16 x i16> %e) {
; CHECK-SD-LABEL: v16i16_i16:
; CHECK-SD: // %bb.0: // %entry
@@ -274,30 +1035,6 @@ entry:
ret <16 x i16> %s
}
-define <8 x i8> @v8i8_i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %d, <8 x i8> %e) {
-; CHECK-LABEL: v8i8_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
-; CHECK-NEXT: ret
-entry:
- %c = icmp slt <8 x i8> %a, %b
- %s = select <8 x i1> %c, <8 x i8> %d, <8 x i8> %e
- ret <8 x i8> %s
-}
-
-define <16 x i8> @v16i8_i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %d, <16 x i8> %e) {
-; CHECK-LABEL: v16i8_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: ret
-entry:
- %c = icmp slt <16 x i8> %a, %b
- %s = select <16 x i1> %c, <16 x i8> %d, <16 x i8> %e
- ret <16 x i8> %s
-}
-
define <32 x i8> @v32i8_i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %d, <32 x i8> %e) {
; CHECK-SD-LABEL: v32i8_i8:
; CHECK-SD: // %bb.0: // %entry
>From b593c0fbefb2ff6330b360b47f464954df959ea4 Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Wed, 17 Apr 2024 14:59:36 +0000
Subject: [PATCH 2/4] [AArch64][GlobalISel] Select G_ICMP instruction through
TableGen
G_ICMP NE => XOR(G_ICMP EQ, -1) moved to Legalizer to allow for
combines if they ever come up in the following passes
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 45 +++
.../GISel/AArch64InstructionSelector.cpp | 174 +--------
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 47 ++-
.../AArch64/GISel/AArch64LegalizerInfo.h | 2 +
.../CodeGen/AArch64/GlobalISel/select-cmp.mir | 4 +-
.../AArch64/GlobalISel/select-vector-icmp.mir | 338 ------------------
6 files changed, 85 insertions(+), 525 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 2159116d1ab7c4..161b56cb7ea49c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5405,6 +5405,51 @@ def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
(BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
+multiclass SelectSetCC<PatFrags InFrag, string INST> {
+ def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
+ (v8i8 (!cast<Instruction>(INST # v8i8) (v8i8 V64:$Rn), (v8i8 V64:$Rm)))>;
+ def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), (v16i8 V128:$Rm))),
+ (v16i8 (!cast<Instruction>(INST # v16i8) (v16i8 V128:$Rn), (v16i8 V128:$Rm)))>;
+ def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
+ (v4i16 (!cast<Instruction>(INST # v4i16) (v4i16 V64:$Rn), (v4i16 V64:$Rm)))>;
+ def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), (v8i16 V128:$Rm))),
+ (v8i16 (!cast<Instruction>(INST # v8i16) (v8i16 V128:$Rn), (v8i16 V128:$Rm)))>;
+ def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
+ (v2i32 (!cast<Instruction>(INST # v2i32) (v2i32 V64:$Rn), (v2i32 V64:$Rm)))>;
+ def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), (v4i32 V128:$Rm))),
+ (v4i32 (!cast<Instruction>(INST # v4i32) (v4i32 V128:$Rn), (v4i32 V128:$Rm)))>;
+ def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), (v2i64 V128:$Rm))),
+ (v2i64 (!cast<Instruction>(INST # v2i64) (v2i64 V128:$Rn), (v2i64 V128:$Rm)))>;
+}
+
+defm : SelectSetCC<seteq, "CMEQ">;
+defm : SelectSetCC<setgt, "CMGT">;
+defm : SelectSetCC<setge, "CMGE">;
+defm : SelectSetCC<setugt, "CMHI">;
+defm : SelectSetCC<setuge, "CMHS">;
+
+multiclass SelectSetCCSwapOperands<PatFrags InFrag, string INST> {
+ def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
+ (v8i8 (!cast<Instruction>(INST # v8i8) (v8i8 V64:$Rm), (v8i8 V64:$Rn)))>;
+ def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), (v16i8 V128:$Rm))),
+ (v16i8 (!cast<Instruction>(INST # v16i8) (v16i8 V128:$Rm), (v16i8 V128:$Rn)))>;
+ def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
+ (v4i16 (!cast<Instruction>(INST # v4i16) (v4i16 V64:$Rm), (v4i16 V64:$Rn)))>;
+ def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), (v8i16 V128:$Rm))),
+ (v8i16 (!cast<Instruction>(INST # v8i16) (v8i16 V128:$Rm), (v8i16 V128:$Rn)))>;
+ def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
+ (v2i32 (!cast<Instruction>(INST # v2i32) (v2i32 V64:$Rm), (v2i32 V64:$Rn)))>;
+ def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), (v4i32 V128:$Rm))),
+ (v4i32 (!cast<Instruction>(INST # v4i32) (v4i32 V128:$Rm), (v4i32 V128:$Rn)))>;
+ def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), (v2i64 V128:$Rm))),
+ (v2i64 (!cast<Instruction>(INST # v2i64) (v2i64 V128:$Rm), (v2i64 V128:$Rn)))>;
+}
+
+defm : SelectSetCCSwapOperands<setlt, "CMGT">;
+defm : SelectSetCCSwapOperands<setle, "CMGE">;
+defm : SelectSetCCSwapOperands<setult, "CMHI">;
+defm : SelectSetCCSwapOperands<setule, "CMHS">;
+
let Predicates = [HasNEON] in {
def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
(ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 61f5bc2464ee54..1b65ae7b47826c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -221,7 +221,6 @@ class AArch64InstructionSelector : public InstructionSelector {
bool selectIntrinsicWithSideEffects(MachineInstr &I,
MachineRegisterInfo &MRI);
bool selectIntrinsic(MachineInstr &I, MachineRegisterInfo &MRI);
- bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI);
bool selectJumpTable(MachineInstr &I, MachineRegisterInfo &MRI);
bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI);
bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI);
@@ -3403,7 +3402,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
}
case TargetOpcode::G_ICMP: {
if (Ty.isVector())
- return selectVectorICmp(I, MRI);
+ return false;
if (Ty != LLT::scalar(32)) {
LLVM_DEBUG(dbgs() << "G_ICMP result has type: " << Ty
@@ -3652,177 +3651,6 @@ bool AArch64InstructionSelector::selectTLSGlobalValue(
return true;
}
-bool AArch64InstructionSelector::selectVectorICmp(
- MachineInstr &I, MachineRegisterInfo &MRI) {
- Register DstReg = I.getOperand(0).getReg();
- LLT DstTy = MRI.getType(DstReg);
- Register SrcReg = I.getOperand(2).getReg();
- Register Src2Reg = I.getOperand(3).getReg();
- LLT SrcTy = MRI.getType(SrcReg);
-
- unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits();
- unsigned NumElts = DstTy.getNumElements();
-
- // First index is element size, 0 == 8b, 1 == 16b, 2 == 32b, 3 == 64b
- // Second index is num elts, 0 == v2, 1 == v4, 2 == v8, 3 == v16
- // Third index is cc opcode:
- // 0 == eq
- // 1 == ugt
- // 2 == uge
- // 3 == ult
- // 4 == ule
- // 5 == sgt
- // 6 == sge
- // 7 == slt
- // 8 == sle
- // ne is done by negating 'eq' result.
-
- // This table below assumes that for some comparisons the operands will be
- // commuted.
- // ult op == commute + ugt op
- // ule op == commute + uge op
- // slt op == commute + sgt op
- // sle op == commute + sge op
- unsigned PredIdx = 0;
- bool SwapOperands = false;
- CmpInst::Predicate Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate();
- switch (Pred) {
- case CmpInst::ICMP_NE:
- case CmpInst::ICMP_EQ:
- PredIdx = 0;
- break;
- case CmpInst::ICMP_UGT:
- PredIdx = 1;
- break;
- case CmpInst::ICMP_UGE:
- PredIdx = 2;
- break;
- case CmpInst::ICMP_ULT:
- PredIdx = 3;
- SwapOperands = true;
- break;
- case CmpInst::ICMP_ULE:
- PredIdx = 4;
- SwapOperands = true;
- break;
- case CmpInst::ICMP_SGT:
- PredIdx = 5;
- break;
- case CmpInst::ICMP_SGE:
- PredIdx = 6;
- break;
- case CmpInst::ICMP_SLT:
- PredIdx = 7;
- SwapOperands = true;
- break;
- case CmpInst::ICMP_SLE:
- PredIdx = 8;
- SwapOperands = true;
- break;
- default:
- llvm_unreachable("Unhandled icmp predicate");
- return false;
- }
-
- // This table obviously should be tablegen'd when we have our GISel native
- // tablegen selector.
-
- static const unsigned OpcTable[4][4][9] = {
- {
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */},
- {AArch64::CMEQv8i8, AArch64::CMHIv8i8, AArch64::CMHSv8i8,
- AArch64::CMHIv8i8, AArch64::CMHSv8i8, AArch64::CMGTv8i8,
- AArch64::CMGEv8i8, AArch64::CMGTv8i8, AArch64::CMGEv8i8},
- {AArch64::CMEQv16i8, AArch64::CMHIv16i8, AArch64::CMHSv16i8,
- AArch64::CMHIv16i8, AArch64::CMHSv16i8, AArch64::CMGTv16i8,
- AArch64::CMGEv16i8, AArch64::CMGTv16i8, AArch64::CMGEv16i8}
- },
- {
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */},
- {AArch64::CMEQv4i16, AArch64::CMHIv4i16, AArch64::CMHSv4i16,
- AArch64::CMHIv4i16, AArch64::CMHSv4i16, AArch64::CMGTv4i16,
- AArch64::CMGEv4i16, AArch64::CMGTv4i16, AArch64::CMGEv4i16},
- {AArch64::CMEQv8i16, AArch64::CMHIv8i16, AArch64::CMHSv8i16,
- AArch64::CMHIv8i16, AArch64::CMHSv8i16, AArch64::CMGTv8i16,
- AArch64::CMGEv8i16, AArch64::CMGTv8i16, AArch64::CMGEv8i16},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */}
- },
- {
- {AArch64::CMEQv2i32, AArch64::CMHIv2i32, AArch64::CMHSv2i32,
- AArch64::CMHIv2i32, AArch64::CMHSv2i32, AArch64::CMGTv2i32,
- AArch64::CMGEv2i32, AArch64::CMGTv2i32, AArch64::CMGEv2i32},
- {AArch64::CMEQv4i32, AArch64::CMHIv4i32, AArch64::CMHSv4i32,
- AArch64::CMHIv4i32, AArch64::CMHSv4i32, AArch64::CMGTv4i32,
- AArch64::CMGEv4i32, AArch64::CMGTv4i32, AArch64::CMGEv4i32},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */}
- },
- {
- {AArch64::CMEQv2i64, AArch64::CMHIv2i64, AArch64::CMHSv2i64,
- AArch64::CMHIv2i64, AArch64::CMHSv2i64, AArch64::CMGTv2i64,
- AArch64::CMGEv2i64, AArch64::CMGTv2i64, AArch64::CMGEv2i64},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */},
- {0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
- 0 /* invalid */}
- },
- };
- unsigned EltIdx = Log2_32(SrcEltSize / 8);
- unsigned NumEltsIdx = Log2_32(NumElts / 2);
- unsigned Opc = OpcTable[EltIdx][NumEltsIdx][PredIdx];
- if (!Opc) {
- LLVM_DEBUG(dbgs() << "Could not map G_ICMP to cmp opcode");
- return false;
- }
-
- const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI);
- const TargetRegisterClass *SrcRC =
- getRegClassForTypeOnBank(SrcTy, VecRB, true);
- if (!SrcRC) {
- LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
- return false;
- }
-
- unsigned NotOpc = Pred == ICmpInst::ICMP_NE ? AArch64::NOTv8i8 : 0;
- if (SrcTy.getSizeInBits() == 128)
- NotOpc = NotOpc ? AArch64::NOTv16i8 : 0;
-
- if (SwapOperands)
- std::swap(SrcReg, Src2Reg);
-
- auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
- constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
-
- // Invert if we had a 'ne' cc.
- if (NotOpc) {
- Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp});
- constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
- } else {
- MIB.buildCopy(DstReg, Cmp.getReg(0));
- }
- RBI.constrainGenericRegister(DstReg, *SrcRC, MRI);
- I.eraseFromParent();
- return true;
-}
-
MachineInstr *AArch64InstructionSelector::emitScalarToVector(
unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,
MachineIRBuilder &MIRBuilder) const {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 24389124966813..a8db80db98c83c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -493,17 +493,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// FIXME: fix moreElementsToNextPow2
getActionDefinitionsBuilder(G_ICMP)
- .legalFor({{s32, s32},
- {s32, s64},
- {s32, p0},
- {v4s32, v4s32},
- {v2s32, v2s32},
- {v2s64, v2s64},
- {v2s64, v2p0},
- {v4s16, v4s16},
- {v8s16, v8s16},
- {v8s8, v8s8},
- {v16s8, v16s8}})
+ .legalFor({{s32, s32}, {s32, s64}, {s32, p0}})
.widenScalarOrEltToNextPow2(1)
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s32)
@@ -525,7 +515,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(1, v8s8, v16s8)
.clampNumElements(1, v4s16, v8s16)
.clampNumElements(1, v2s32, v4s32)
- .clampNumElements(1, v2s64, v2s64);
+ .clampNumElements(1, v2s64, v2s64)
+ .customIf(isVector(0));
getActionDefinitionsBuilder(G_FCMP)
.legalFor({{s32, MinFPScalar},
@@ -1264,6 +1255,8 @@ bool AArch64LegalizerInfo::legalizeCustom(
return legalizePrefetch(MI, Helper);
case TargetOpcode::G_ABS:
return Helper.lowerAbsToCNeg(MI);
+ case TargetOpcode::G_ICMP:
+ return legalizeICMP(MI, MRI, MIRBuilder);
}
llvm_unreachable("expected switch to return");
@@ -1322,6 +1315,36 @@ bool AArch64LegalizerInfo::legalizeFunnelShift(MachineInstr &MI,
return true;
}
+bool AArch64LegalizerInfo::legalizeICMP(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ MachineIRBuilder &MIRBuilder) const {
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg1 = MI.getOperand(2).getReg();
+ Register SrcReg2 = MI.getOperand(3).getReg();
+ LLT DstTy = MRI.getType(DstReg);
+ LLT SrcTy = MRI.getType(SrcReg1);
+
+ // Check the vector types are legal
+ if (DstTy.getScalarSizeInBits() != SrcTy.getScalarSizeInBits() ||
+ DstTy.getNumElements() != SrcTy.getNumElements() ||
+ (DstTy.getSizeInBits() != 64 && DstTy.getSizeInBits() != 128))
+ return false;
+
+ // Lowers G_ICMP NE => G_ICMP EQ to allow better pattern matching for
+ // following passes
+ CmpInst::Predicate Pred = (CmpInst::Predicate)MI.getOperand(1).getPredicate();
+ if (Pred != CmpInst::ICMP_NE)
+ return true;
+ Register CmpReg =
+ MIRBuilder
+ .buildICmp(CmpInst::ICMP_EQ, MRI.getType(DstReg), SrcReg1, SrcReg2)
+ .getReg(0);
+ MIRBuilder.buildNot(DstReg, CmpReg);
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool AArch64LegalizerInfo::legalizeRotate(MachineInstr &MI,
MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
index b69d9b015bd2b3..00d85a36e4b2ca 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
@@ -50,6 +50,8 @@ class AArch64LegalizerInfo : public LegalizerInfo {
LegalizerHelper &Helper) const;
bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
+ bool legalizeICMP(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &MIRBuilder) const;
bool legalizeFunnelShift(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
index 4151f7ecb3eacf..df4e7ddaac8b94 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
@@ -361,8 +361,8 @@ body: |
; CHECK-NEXT: %cmp_lhs:fpr128 = COPY $q0
; CHECK-NEXT: %cmp_rhs:fpr128 = COPY $q1
; CHECK-NEXT: %add_lhs:fpr128 = COPY $q2
- ; CHECK-NEXT: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs
- ; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, [[CMEQv4i32_]]
+ ; CHECK-NEXT: %cmp:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs
+ ; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, %cmp
; CHECK-NEXT: $q0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $q0
%cmp_lhs:fpr(<4 x s32>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
index 21e84ecaed32f9..7884d9e1b1d72c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
@@ -46,46 +46,6 @@
ret <8 x i1> %cmp
}
- define <2 x i1> @test_v2i64_ne(<2 x i64> %v1, <2 x i64> %v2) {
- %cmp = icmp ne <2 x i64> %v1, %v2
- ret <2 x i1> %cmp
- }
-
- define <4 x i1> @test_v4i32_ne(<4 x i32> %v1, <4 x i32> %v2) {
- %cmp = icmp ne <4 x i32> %v1, %v2
- ret <4 x i1> %cmp
- }
-
- define <2 x i1> @test_v2i32_ne(<2 x i32> %v1, <2 x i32> %v2) {
- %cmp = icmp ne <2 x i32> %v1, %v2
- ret <2 x i1> %cmp
- }
-
- define <2 x i1> @test_v2i16_ne(<2 x i16> %v1, <2 x i16> %v2) {
- %cmp = icmp ne <2 x i16> %v1, %v2
- ret <2 x i1> %cmp
- }
-
- define <8 x i1> @test_v8i16_ne(<8 x i16> %v1, <8 x i16> %v2) {
- %cmp = icmp ne <8 x i16> %v1, %v2
- ret <8 x i1> %cmp
- }
-
- define <4 x i1> @test_v4i16_ne(<4 x i16> %v1, <4 x i16> %v2) {
- %cmp = icmp ne <4 x i16> %v1, %v2
- ret <4 x i1> %cmp
- }
-
- define <16 x i1> @test_v16i8_ne(<16 x i8> %v1, <16 x i8> %v2) {
- %cmp = icmp ne <16 x i8> %v1, %v2
- ret <16 x i1> %cmp
- }
-
- define <8 x i1> @test_v8i8_ne(<8 x i8> %v1, <8 x i8> %v2) {
- %cmp = icmp ne <8 x i8> %v1, %v2
- ret <8 x i1> %cmp
- }
-
define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) {
%cmp = icmp ugt <2 x i64> %v1, %v2
ret <2 x i1> %cmp
@@ -696,304 +656,6 @@ body: |
$d0 = COPY %3(<8 x s8>)
RET_ReallyLR implicit $d0
-...
----
-name: test_v2i64_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $q0, $q1
-
- ; CHECK-LABEL: name: test_v2i64_ne
- ; CHECK: liveins: $q0, $q1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
- ; CHECK-NEXT: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv2i64_]]
- ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[NOTv16i8_]]
- ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(ne), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
- RET_ReallyLR implicit $d0
-
-...
----
-name: test_v4i32_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $q0, $q1
-
- ; CHECK-LABEL: name: test_v4i32_ne
- ; CHECK: liveins: $q0, $q1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
- ; CHECK-NEXT: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv4i32_]]
- ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[NOTv16i8_]]
- ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(ne), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
- RET_ReallyLR implicit $d0
-
-...
----
-name: test_v2i32_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $d0, $d1
-
- ; CHECK-LABEL: name: test_v2i32_ne
- ; CHECK: liveins: $d0, $d1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv2i32_]]
- ; CHECK-NEXT: $d0 = COPY [[NOTv8i8_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(ne), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
- RET_ReallyLR implicit $d0
-
-...
----
-name: test_v2i16_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: fpr }
- - { id: 3, class: fpr }
- - { id: 4, class: _ }
- - { id: 5, class: fpr }
- - { id: 6, class: _ }
- - { id: 7, class: fpr }
- - { id: 8, class: fpr }
- - { id: 9, class: fpr }
- - { id: 10, class: gpr }
- - { id: 11, class: fpr }
- - { id: 12, class: fpr }
- - { id: 13, class: gpr }
- - { id: 14, class: fpr }
- - { id: 15, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $d0, $d1
-
- ; CHECK-LABEL: name: test_v2i16_ne
- ; CHECK: liveins: $d0, $d1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51
- ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]]
- ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51
- ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]]
- ; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
- ; CHECK-NEXT: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv2i32_]]
- ; CHECK-NEXT: $d0 = COPY [[NOTv8i8_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
- %13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
- %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %7:fpr(<2 x s32>) = G_AND %15, %14
- %10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %8:fpr(<2 x s32>) = G_AND %12, %11
- %9:fpr(<2 x s32>) = G_ICMP intpred(ne), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
- RET_ReallyLR implicit $d0
-
-...
----
-name: test_v8i16_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $q0, $q1
-
- ; CHECK-LABEL: name: test_v8i16_ne
- ; CHECK: liveins: $q0, $q1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
- ; CHECK-NEXT: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv8i16_]]
- ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[NOTv16i8_]]
- ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(ne), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
- RET_ReallyLR implicit $d0
-
-...
----
-name: test_v4i16_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $d0, $d1
-
- ; CHECK-LABEL: name: test_v4i16_ne
- ; CHECK: liveins: $d0, $d1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv4i16_]]
- ; CHECK-NEXT: $d0 = COPY [[NOTv8i8_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(ne), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
- RET_ReallyLR implicit $d0
-
-...
----
-name: test_v16i8_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $q0, $q1
-
- ; CHECK-LABEL: name: test_v16i8_ne
- ; CHECK: liveins: $q0, $q1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
- ; CHECK-NEXT: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv16i8_]]
- ; CHECK-NEXT: $q0 = COPY [[NOTv16i8_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(ne), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
- RET_ReallyLR implicit $q0
-
-...
----
-name: test_v8i8_ne
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: _ }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
-machineFunctionInfo: {}
-body: |
- bb.1 (%ir-block.0):
- liveins: $d0, $d1
-
- ; CHECK-LABEL: name: test_v8i8_ne
- ; CHECK: liveins: $d0, $d1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv8i8_]]
- ; CHECK-NEXT: $d0 = COPY [[NOTv8i8_]]
- ; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(ne), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
- RET_ReallyLR implicit $d0
-
...
---
name: test_v2i64_ugt
>From 45b3dd055f8c400f5626a0b796ee993ddba160fe Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 25 Apr 2024 08:55:08 +0000
Subject: [PATCH 3/4] [AArch64][GlobalISel] Pre-commit Tests for Select G_ICMP
Zero Instruction
---
llvm/test/CodeGen/AArch64/icmp.ll | 1114 +++++++++++++++++++++++++++++
1 file changed, 1114 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 4e2c62fbd4539a..cfdea42fea07a9 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -1056,3 +1056,1117 @@ entry:
%s = select <32 x i1> %c, <32 x i8> %d, <32 x i8> %e
ret <32 x i8> %s
}
+
+; ===== ICMP Zero RHS =====
+
+define <8 x i1> @icmp_eq_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_eq_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_eq_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sge_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sgt_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sle_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_slt_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+; ===== ICMP Zero LHS =====
+
+define <8 x i1> @icmp_eq_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_eq_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_eq_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sge_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sgt_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sle_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_slt_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
>From 2d7afdd2c9d7a515adc818597a8f202cbe48d87d Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 25 Apr 2024 12:26:43 +0000
Subject: [PATCH 4/4] [AArch64][GlobalISel] Select G_ICMP Zero Instruction
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 46 +
llvm/test/CodeGen/AArch64/aarch64-addv.ll | 25 +-
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 227 ++--
llvm/test/CodeGen/AArch64/icmp.ll | 1070 +++++------------
.../AArch64/neon-bitwise-instructions.ll | 43 +-
.../AArch64/neon-compare-instructions.ll | 532 +++-----
6 files changed, 640 insertions(+), 1303 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 161b56cb7ea49c..8b2ef0a30c5756 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5450,6 +5450,52 @@ defm : SelectSetCCSwapOperands<setle, "CMGE">;
defm : SelectSetCCSwapOperands<setult, "CMHI">;
defm : SelectSetCCSwapOperands<setule, "CMHS">;
+multiclass SelectSetCCZeroRHS<PatFrags InFrag, string INST> {
+ def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), immAllZerosV)),
+ (v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;
+ def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), immAllZerosV)),
+ (v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;
+ def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), immAllZerosV)),
+ (v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;
+ def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), immAllZerosV)),
+ (v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;
+ def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), immAllZerosV)),
+ (v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;
+ def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), immAllZerosV)),
+ (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
+ def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), immAllZerosV)),
+ (v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;
+}
+
+defm : SelectSetCCZeroRHS<seteq, "CMEQ">;
+defm : SelectSetCCZeroRHS<setgt, "CMGT">;
+defm : SelectSetCCZeroRHS<setge, "CMGE">;
+defm : SelectSetCCZeroRHS<setlt, "CMLT">;
+defm : SelectSetCCZeroRHS<setle, "CMLE">;
+
+multiclass SelectSetCCZeroLHS<PatFrags InFrag, string INST> {
+ def : Pat<(v8i8 (InFrag immAllZerosV, (v8i8 V64:$Rn))),
+ (v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;
+ def : Pat<(v16i8 (InFrag immAllZerosV, (v16i8 V128:$Rn))),
+ (v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;
+ def : Pat<(v4i16 (InFrag immAllZerosV, (v4i16 V64:$Rn))),
+ (v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;
+ def : Pat<(v8i16 (InFrag immAllZerosV, (v8i16 V128:$Rn))),
+ (v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;
+ def : Pat<(v2i32 (InFrag immAllZerosV, (v2i32 V64:$Rn))),
+ (v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;
+ def : Pat<(v4i32 (InFrag immAllZerosV, (v4i32 V128:$Rn))),
+ (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
+ def : Pat<(v2i64 (InFrag immAllZerosV, (v2i64 V128:$Rn))),
+ (v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;
+}
+
+defm : SelectSetCCZeroLHS<seteq, "CMEQ">;
+defm : SelectSetCCZeroLHS<setgt, "CMLT">;
+defm : SelectSetCCZeroLHS<setge, "CMLE">;
+defm : SelectSetCCZeroLHS<setlt, "CMGT">;
+defm : SelectSetCCZeroLHS<setle, "CMGE">;
+
let Predicates = [HasNEON] in {
def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
(ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
diff --git a/llvm/test/CodeGen/AArch64/aarch64-addv.ll b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
index ee035ec1941d57..94b792b887eb47 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-addv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
@@ -94,20 +94,19 @@ define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias
;
; GISEL-LABEL: oversized_ADDV_256:
; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: movi v0.2d, #0000000000000000
+; GISEL-NEXT: ldr d0, [x0]
+; GISEL-NEXT: ldr d1, [x1]
+; GISEL-NEXT: ushll v0.8h, v0.8b, #0
; GISEL-NEXT: ushll v1.8h, v1.8b, #0
-; GISEL-NEXT: ushll v2.8h, v2.8b, #0
-; GISEL-NEXT: usubl v3.4s, v1.4h, v2.4h
-; GISEL-NEXT: usubl2 v1.4s, v1.8h, v2.8h
-; GISEL-NEXT: cmgt v2.4s, v0.4s, v3.4s
-; GISEL-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; GISEL-NEXT: neg v4.4s, v3.4s
-; GISEL-NEXT: neg v5.4s, v1.4s
-; GISEL-NEXT: bsl v2.16b, v4.16b, v3.16b
-; GISEL-NEXT: bsl v0.16b, v5.16b, v1.16b
-; GISEL-NEXT: add v0.4s, v2.4s, v0.4s
+; GISEL-NEXT: usubl v2.4s, v0.4h, v1.4h
+; GISEL-NEXT: usubl2 v0.4s, v0.8h, v1.8h
+; GISEL-NEXT: cmlt v1.4s, v2.4s, #0
+; GISEL-NEXT: cmlt v3.4s, v0.4s, #0
+; GISEL-NEXT: neg v4.4s, v2.4s
+; GISEL-NEXT: neg v5.4s, v0.4s
+; GISEL-NEXT: bsl v1.16b, v4.16b, v2.16b
+; GISEL-NEXT: bit v0.16b, v5.16b, v3.16b
+; GISEL-NEXT: add v0.4s, v1.4s, v0.4s
; GISEL-NEXT: addv s0, v0.4s
; GISEL-NEXT: fmov w0, s0
; GISEL-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index d64327656a9e01..f7d31a214563bc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -252,18 +252,17 @@ define i16 @uabd16b_rdx(ptr %a, ptr %b) {
;
; CHECK-GI-LABEL: uabd16b_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr q1, [x0]
-; CHECK-GI-NEXT: ldr q2, [x1]
-; CHECK-GI-NEXT: movi.2d v0, #0000000000000000
-; CHECK-GI-NEXT: usubl.8h v3, v1, v2
-; CHECK-GI-NEXT: usubl2.8h v1, v1, v2
-; CHECK-GI-NEXT: cmgt.8h v2, v0, v3
-; CHECK-GI-NEXT: cmgt.8h v0, v0, v1
-; CHECK-GI-NEXT: neg.8h v4, v3
-; CHECK-GI-NEXT: neg.8h v5, v1
-; CHECK-GI-NEXT: bsl.16b v2, v4, v3
-; CHECK-GI-NEXT: bsl.16b v0, v5, v1
-; CHECK-GI-NEXT: add.8h v0, v2, v0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: usubl.8h v2, v0, v1
+; CHECK-GI-NEXT: usubl2.8h v0, v0, v1
+; CHECK-GI-NEXT: cmlt.8h v1, v2, #0
+; CHECK-GI-NEXT: cmlt.8h v3, v0, #0
+; CHECK-GI-NEXT: neg.8h v4, v2
+; CHECK-GI-NEXT: neg.8h v5, v0
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
+; CHECK-GI-NEXT: add.8h v0, v1, v0
; CHECK-GI-NEXT: addv.8h h0, v0
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
@@ -290,29 +289,28 @@ define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: uabd16b_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll.8h v3, v0, #0
-; CHECK-GI-NEXT: ushll.8h v4, v1, #0
+; CHECK-GI-NEXT: ushll.8h v2, v0, #0
+; CHECK-GI-NEXT: ushll.8h v3, v1, #0
; CHECK-GI-NEXT: ushll2.8h v0, v0, #0
; CHECK-GI-NEXT: ushll2.8h v1, v1, #0
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: usubl.4s v5, v3, v4
-; CHECK-GI-NEXT: usubl2.4s v3, v3, v4
-; CHECK-GI-NEXT: usubl.4s v4, v0, v1
+; CHECK-GI-NEXT: usubl.4s v4, v2, v3
+; CHECK-GI-NEXT: usubl2.4s v2, v2, v3
+; CHECK-GI-NEXT: usubl.4s v3, v0, v1
; CHECK-GI-NEXT: usubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v5
-; CHECK-GI-NEXT: cmgt.4s v6, v2, v3
-; CHECK-GI-NEXT: neg.4s v16, v5
-; CHECK-GI-NEXT: cmgt.4s v7, v2, v4
-; CHECK-GI-NEXT: cmgt.4s v2, v2, v0
-; CHECK-GI-NEXT: neg.4s v17, v3
-; CHECK-GI-NEXT: neg.4s v18, v4
+; CHECK-GI-NEXT: cmlt.4s v1, v4, #0
+; CHECK-GI-NEXT: cmlt.4s v5, v2, #0
+; CHECK-GI-NEXT: neg.4s v16, v4
+; CHECK-GI-NEXT: cmlt.4s v6, v3, #0
+; CHECK-GI-NEXT: cmlt.4s v7, v0, #0
+; CHECK-GI-NEXT: neg.4s v17, v2
+; CHECK-GI-NEXT: neg.4s v18, v3
; CHECK-GI-NEXT: neg.4s v19, v0
-; CHECK-GI-NEXT: bsl.16b v1, v16, v5
-; CHECK-GI-NEXT: bit.16b v3, v17, v6
-; CHECK-GI-NEXT: bit.16b v4, v18, v7
-; CHECK-GI-NEXT: bit.16b v0, v19, v2
-; CHECK-GI-NEXT: add.4s v1, v1, v3
-; CHECK-GI-NEXT: add.4s v0, v4, v0
+; CHECK-GI-NEXT: bsl.16b v1, v16, v4
+; CHECK-GI-NEXT: bit.16b v2, v17, v5
+; CHECK-GI-NEXT: bit.16b v3, v18, v6
+; CHECK-GI-NEXT: bit.16b v0, v19, v7
+; CHECK-GI-NEXT: add.4s v1, v1, v2
+; CHECK-GI-NEXT: add.4s v0, v3, v0
; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
@@ -338,29 +336,28 @@ define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: sabd16b_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll.8h v3, v0, #0
-; CHECK-GI-NEXT: sshll.8h v4, v1, #0
+; CHECK-GI-NEXT: sshll.8h v2, v0, #0
+; CHECK-GI-NEXT: sshll.8h v3, v1, #0
; CHECK-GI-NEXT: sshll2.8h v0, v0, #0
; CHECK-GI-NEXT: sshll2.8h v1, v1, #0
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: ssubl.4s v5, v3, v4
-; CHECK-GI-NEXT: ssubl2.4s v3, v3, v4
-; CHECK-GI-NEXT: ssubl.4s v4, v0, v1
+; CHECK-GI-NEXT: ssubl.4s v4, v2, v3
+; CHECK-GI-NEXT: ssubl2.4s v2, v2, v3
+; CHECK-GI-NEXT: ssubl.4s v3, v0, v1
; CHECK-GI-NEXT: ssubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v5
-; CHECK-GI-NEXT: cmgt.4s v6, v2, v3
-; CHECK-GI-NEXT: neg.4s v16, v5
-; CHECK-GI-NEXT: cmgt.4s v7, v2, v4
-; CHECK-GI-NEXT: cmgt.4s v2, v2, v0
-; CHECK-GI-NEXT: neg.4s v17, v3
-; CHECK-GI-NEXT: neg.4s v18, v4
+; CHECK-GI-NEXT: cmlt.4s v1, v4, #0
+; CHECK-GI-NEXT: cmlt.4s v5, v2, #0
+; CHECK-GI-NEXT: neg.4s v16, v4
+; CHECK-GI-NEXT: cmlt.4s v6, v3, #0
+; CHECK-GI-NEXT: cmlt.4s v7, v0, #0
+; CHECK-GI-NEXT: neg.4s v17, v2
+; CHECK-GI-NEXT: neg.4s v18, v3
; CHECK-GI-NEXT: neg.4s v19, v0
-; CHECK-GI-NEXT: bsl.16b v1, v16, v5
-; CHECK-GI-NEXT: bit.16b v3, v17, v6
-; CHECK-GI-NEXT: bit.16b v4, v18, v7
-; CHECK-GI-NEXT: bit.16b v0, v19, v2
-; CHECK-GI-NEXT: add.4s v1, v1, v3
-; CHECK-GI-NEXT: add.4s v0, v4, v0
+; CHECK-GI-NEXT: bsl.16b v1, v16, v4
+; CHECK-GI-NEXT: bit.16b v2, v17, v5
+; CHECK-GI-NEXT: bit.16b v3, v18, v6
+; CHECK-GI-NEXT: bit.16b v0, v19, v7
+; CHECK-GI-NEXT: add.4s v1, v1, v2
+; CHECK-GI-NEXT: add.4s v0, v3, v0
; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
@@ -391,18 +388,17 @@ define i32 @uabd8h_rdx(ptr %a, ptr %b) {
;
; CHECK-GI-LABEL: uabd8h_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr q1, [x0]
-; CHECK-GI-NEXT: ldr q2, [x1]
-; CHECK-GI-NEXT: movi.2d v0, #0000000000000000
-; CHECK-GI-NEXT: usubl.4s v3, v1, v2
-; CHECK-GI-NEXT: usubl2.4s v1, v1, v2
-; CHECK-GI-NEXT: cmgt.4s v2, v0, v3
-; CHECK-GI-NEXT: cmgt.4s v0, v0, v1
-; CHECK-GI-NEXT: neg.4s v4, v3
-; CHECK-GI-NEXT: neg.4s v5, v1
-; CHECK-GI-NEXT: bsl.16b v2, v4, v3
-; CHECK-GI-NEXT: bsl.16b v0, v5, v1
-; CHECK-GI-NEXT: add.4s v0, v2, v0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: usubl.4s v2, v0, v1
+; CHECK-GI-NEXT: usubl2.4s v0, v0, v1
+; CHECK-GI-NEXT: cmlt.4s v1, v2, #0
+; CHECK-GI-NEXT: cmlt.4s v3, v0, #0
+; CHECK-GI-NEXT: neg.4s v4, v2
+; CHECK-GI-NEXT: neg.4s v5, v0
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
+; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
@@ -428,15 +424,14 @@ define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
;
; CHECK-GI-LABEL: sabd8h_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: ssubl.4s v3, v0, v1
+; CHECK-GI-NEXT: ssubl.4s v2, v0, v1
; CHECK-GI-NEXT: ssubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: neg.4s v4, v3
+; CHECK-GI-NEXT: cmlt.4s v1, v2, #0
+; CHECK-GI-NEXT: cmlt.4s v3, v0, #0
+; CHECK-GI-NEXT: neg.4s v4, v2
; CHECK-GI-NEXT: neg.4s v5, v0
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v3
-; CHECK-GI-NEXT: cmgt.4s v2, v2, v0
-; CHECK-GI-NEXT: bsl.16b v1, v4, v3
-; CHECK-GI-NEXT: bit.16b v0, v5, v2
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
@@ -461,9 +456,8 @@ define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
;
; CHECK-GI-LABEL: uabdl4s_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
; CHECK-GI-NEXT: usubl.4s v0, v0, v1
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v0
+; CHECK-GI-NEXT: cmlt.4s v1, v0, #0
; CHECK-GI-NEXT: neg.4s v2, v0
; CHECK-GI-NEXT: bit.16b v0, v2, v1
; CHECK-GI-NEXT: addv.4s s0, v0
@@ -494,18 +488,17 @@ define i64 @uabd4s_rdx(ptr %a, ptr %b, i32 %h) {
;
; CHECK-GI-LABEL: uabd4s_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr q1, [x0]
-; CHECK-GI-NEXT: ldr q2, [x1]
-; CHECK-GI-NEXT: movi.2d v0, #0000000000000000
-; CHECK-GI-NEXT: usubl.2d v3, v1, v2
-; CHECK-GI-NEXT: usubl2.2d v1, v1, v2
-; CHECK-GI-NEXT: cmgt.2d v2, v0, v3
-; CHECK-GI-NEXT: cmgt.2d v0, v0, v1
-; CHECK-GI-NEXT: neg.2d v4, v3
-; CHECK-GI-NEXT: neg.2d v5, v1
-; CHECK-GI-NEXT: bsl.16b v2, v4, v3
-; CHECK-GI-NEXT: bsl.16b v0, v5, v1
-; CHECK-GI-NEXT: add.2d v0, v2, v0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: usubl.2d v2, v0, v1
+; CHECK-GI-NEXT: usubl2.2d v0, v0, v1
+; CHECK-GI-NEXT: cmlt.2d v1, v2, #0
+; CHECK-GI-NEXT: cmlt.2d v3, v0, #0
+; CHECK-GI-NEXT: neg.2d v4, v2
+; CHECK-GI-NEXT: neg.2d v5, v0
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
+; CHECK-GI-NEXT: add.2d v0, v1, v0
; CHECK-GI-NEXT: addp.2d d0, v0
; CHECK-GI-NEXT: fmov x0, d0
; CHECK-GI-NEXT: ret
@@ -531,15 +524,14 @@ define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: sabd4s_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: ssubl.2d v3, v0, v1
+; CHECK-GI-NEXT: ssubl.2d v2, v0, v1
; CHECK-GI-NEXT: ssubl2.2d v0, v0, v1
-; CHECK-GI-NEXT: neg.2d v4, v3
+; CHECK-GI-NEXT: cmlt.2d v1, v2, #0
+; CHECK-GI-NEXT: cmlt.2d v3, v0, #0
+; CHECK-GI-NEXT: neg.2d v4, v2
; CHECK-GI-NEXT: neg.2d v5, v0
-; CHECK-GI-NEXT: cmgt.2d v1, v2, v3
-; CHECK-GI-NEXT: cmgt.2d v2, v2, v0
-; CHECK-GI-NEXT: bsl.16b v1, v4, v3
-; CHECK-GI-NEXT: bit.16b v0, v5, v2
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
; CHECK-GI-NEXT: add.2d v0, v1, v0
; CHECK-GI-NEXT: addp.2d d0, v0
; CHECK-GI-NEXT: fmov x0, d0
@@ -564,9 +556,8 @@ define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
;
; CHECK-GI-LABEL: uabdl2d_rdx_i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
; CHECK-GI-NEXT: usubl.2d v0, v0, v1
-; CHECK-GI-NEXT: cmgt.2d v1, v2, v0
+; CHECK-GI-NEXT: cmlt.2d v1, v0, #0
; CHECK-GI-NEXT: neg.2d v2, v0
; CHECK-GI-NEXT: bit.16b v0, v2, v1
; CHECK-GI-NEXT: addp.2d d0, v0
@@ -1662,10 +1653,9 @@ define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern1:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.2s v2, v0
-; CHECK-GI-NEXT: cmge.2s v1, v0, v1
-; CHECK-GI-NEXT: bif.8b v0, v2, v1
+; CHECK-GI-NEXT: neg.2s v1, v0
+; CHECK-GI-NEXT: cmge.2s v2, v0, #0
+; CHECK-GI-NEXT: bif.8b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sge <2 x i32> %a, zeroinitializer
@@ -1682,10 +1672,9 @@ define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.4h v2, v0
-; CHECK-GI-NEXT: cmgt.4h v1, v0, v1
-; CHECK-GI-NEXT: bif.8b v0, v2, v1
+; CHECK-GI-NEXT: neg.4h v1, v0
+; CHECK-GI-NEXT: cmgt.4h v2, v0, #0
+; CHECK-GI-NEXT: bif.8b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <4 x i16> zeroinitializer, %a
%b = icmp sgt <4 x i16> %a, zeroinitializer
@@ -1701,10 +1690,9 @@ define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.8b v2, v0
-; CHECK-GI-NEXT: cmgt.8b v1, v1, v0
-; CHECK-GI-NEXT: bit.8b v0, v2, v1
+; CHECK-GI-NEXT: neg.8b v1, v0
+; CHECK-GI-NEXT: cmlt.8b v2, v0, #0
+; CHECK-GI-NEXT: bit.8b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <8 x i8> zeroinitializer, %a
%b = icmp slt <8 x i8> %a, zeroinitializer
@@ -1720,10 +1708,9 @@ define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern4:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.4s v2, v0
-; CHECK-GI-NEXT: cmge.4s v1, v0, v1
-; CHECK-GI-NEXT: bif.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.4s v1, v0
+; CHECK-GI-NEXT: cmge.4s v2, v0, #0
+; CHECK-GI-NEXT: bif.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sge <4 x i32> %a, zeroinitializer
@@ -1739,10 +1726,9 @@ define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern5:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.8h v2, v0
-; CHECK-GI-NEXT: cmgt.8h v1, v0, v1
-; CHECK-GI-NEXT: bif.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.8h v1, v0
+; CHECK-GI-NEXT: cmgt.8h v2, v0, #0
+; CHECK-GI-NEXT: bif.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <8 x i16> zeroinitializer, %a
%b = icmp sgt <8 x i16> %a, zeroinitializer
@@ -1758,10 +1744,9 @@ define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern6:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.16b v2, v0
-; CHECK-GI-NEXT: cmgt.16b v1, v1, v0
-; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.16b v1, v0
+; CHECK-GI-NEXT: cmlt.16b v2, v0, #0
+; CHECK-GI-NEXT: bit.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <16 x i8> zeroinitializer, %a
%b = icmp slt <16 x i8> %a, zeroinitializer
@@ -1777,10 +1762,9 @@ define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern7:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.2d v2, v0
-; CHECK-GI-NEXT: cmge.2d v1, v1, v0
-; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.2d v1, v0
+; CHECK-GI-NEXT: cmle.2d v2, v0, #0
+; CHECK-GI-NEXT: bit.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <2 x i64> zeroinitializer, %a
%b = icmp sle <2 x i64> %a, zeroinitializer
@@ -1796,9 +1780,8 @@ define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
;
; CHECK-GI-LABEL: uabd_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
; CHECK-GI-NEXT: ssubl.2d v0, v0, v1
-; CHECK-GI-NEXT: cmgt.2d v1, v2, v0
+; CHECK-GI-NEXT: cmlt.2d v1, v0, #0
; CHECK-GI-NEXT: neg.2d v2, v0
; CHECK-GI-NEXT: bit.16b v0, v2, v1
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index cfdea42fea07a9..c4ebe266b0f7e4 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -1060,556 +1060,331 @@ entry:
; ===== ICMP Zero RHS =====
define <8 x i1> @icmp_eq_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp eq <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_eq_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp eq <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_eq_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_eq_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp eq <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_eq_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp eq <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_eq_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp eq <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_eq_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp eq <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_sge_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sge <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_sge_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sge <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_sge_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sge <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_sge_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sge <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_sge_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sge <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_sge_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sge <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_sge_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sge <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_sgt_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_sle_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sle <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_sle_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sle <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_sle_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sle <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_sle_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sle <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_sle_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sle <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_sle_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sle <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_sle_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sle <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_slt_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp slt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_slt_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp slt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_slt_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp slt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_slt_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp slt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_slt_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp slt <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_slt_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp slt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp slt <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
@@ -1617,556 +1392,331 @@ define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {
; ===== ICMP Zero LHS =====
define <8 x i1> @icmp_eq_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp eq <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_eq_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp eq <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_eq_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp eq <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_eq_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp eq <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_eq_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp eq <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_eq_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp eq <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_eq_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp eq <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_sge_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sge <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_sge_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sge <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_sge_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sge <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_sge_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sge <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_sge_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sge <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_sge_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sge <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_sge_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sge <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_sgt_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_sle_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sle <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_sle_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sle <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_sle_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sle <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_sle_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sle <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_sle_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sle <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_sle_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sle <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_sle_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sle <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_slt_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp slt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_slt_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp slt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_slt_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp slt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_slt_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp slt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_slt_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp slt <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_slt_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp slt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_slt_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp slt <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index 57f220f621cf8b..50c0c8b11e7517 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -1513,8 +1513,7 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
;
; CHECK-GI-LABEL: vselect_cmpz_ne:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
; CHECK-GI-NEXT: ret
@@ -1524,38 +1523,23 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
}
define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
-; CHECK-SD-LABEL: vselect_cmpz_eq:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vselect_cmpz_eq:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
-; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vselect_cmpz_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%cmp = icmp eq <8 x i8> %a, zeroinitializer
%d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
ret <8 x i8> %d
}
define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
-; CHECK-SD-LABEL: vselect_tst:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vselect_tst:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
-; CHECK-GI-NEXT: bsl v0.8b, v2.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vselect_tst:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b
+; CHECK-NEXT: ret
%tmp3 = and <8 x i8> %a, %b
%tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
%d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
@@ -1570,9 +1554,8 @@ define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
;
; CHECK-GI-LABEL: sext_tst:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = and <8 x i8> %a, %b
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index dbb5dfebd44abc..59958afdd0d1e9 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -745,9 +745,8 @@ define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
;
; CHECK-GI-LABEL: cmtst8xi8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = and <8 x i8> %A, %B
@@ -764,9 +763,8 @@ define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
;
; CHECK-GI-LABEL: cmtst16xi8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = and <16 x i8> %A, %B
@@ -783,9 +781,8 @@ define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
;
; CHECK-GI-LABEL: cmtst4xi16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v2.4h
+; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = and <4 x i16> %A, %B
@@ -802,9 +799,8 @@ define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
;
; CHECK-GI-LABEL: cmtst8xi16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = and <8 x i16> %A, %B
@@ -821,9 +817,8 @@ define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
;
; CHECK-GI-LABEL: cmtst2xi32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v2.2s
+; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = and <2 x i32> %A, %B
@@ -840,9 +835,8 @@ define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
;
; CHECK-GI-LABEL: cmtst4xi32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = and <4 x i32> %A, %B
@@ -859,9 +853,8 @@ define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
;
; CHECK-GI-LABEL: cmtst2xi64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = and <2 x i64> %A, %B
@@ -873,112 +866,70 @@ define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmeqz8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmeqz16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmeqz4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmeqz8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmeqz2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmeqz4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmeqz2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -986,112 +937,70 @@ define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmgez8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmgez16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmgez4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmgez8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmgez2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmgez4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmgez2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -1324,224 +1233,140 @@ define <2 x i64> @cmgez2xi64_alt2(<2 x i64> %A) {
define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmgtz8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmgtz16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmgtz4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmgtz8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmgtz2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmgtz4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmgtz2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
}
define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmlez8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmlez16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmlez4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmlez8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmlez2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmlez4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmlez2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -1661,112 +1486,70 @@ define <2 x i64> @cmlez2xi64_alt(<2 x i64> %A) {
}
define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmltz8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmltz16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmltz4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmltz8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmltz2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmltz4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmltz2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -1916,8 +1699,7 @@ define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
;
; CHECK-GI-LABEL: cmneqz8xi8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <8 x i8> %A, zeroinitializer
@@ -1933,8 +1715,7 @@ define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
;
; CHECK-GI-LABEL: cmneqz16xi8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <16 x i8> %A, zeroinitializer
@@ -1950,8 +1731,7 @@ define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
;
; CHECK-GI-LABEL: cmneqz4xi16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <4 x i16> %A, zeroinitializer
@@ -1967,8 +1747,7 @@ define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
;
; CHECK-GI-LABEL: cmneqz8xi16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <8 x i16> %A, zeroinitializer
@@ -1984,8 +1763,7 @@ define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
;
; CHECK-GI-LABEL: cmneqz2xi32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, #0
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <2 x i32> %A, zeroinitializer
@@ -2001,8 +1779,7 @@ define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
;
; CHECK-GI-LABEL: cmneqz4xi32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <4 x i32> %A, zeroinitializer
@@ -2018,8 +1795,7 @@ define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
;
; CHECK-GI-LABEL: cmneqz2xi64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, #0
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
; CHECK-GI-NEXT: ret
%tmp3 = icmp ne <2 x i64> %A, zeroinitializer
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