[llvm] [RISCV][ISel] Combine scalable vector fadd/fsub/fmul with fp extend. (PR #88615)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 22:49:31 PDT 2024
================
@@ -13597,6 +13599,13 @@ struct NodeExtensionHelper {
case RISCVISD::VZEXT_VL:
case RISCVISD::FP_EXTEND_VL:
return OrigOperand.getOperand(0);
+ case ISD::SPLAT_VECTOR: {
+ SDValue Op = OrigOperand.getOperand(0);
+ if (Op.getOpcode() == ISD::FP_EXTEND)
+ return Op;
----------------
sun-jacobi wrote:
> Why do we need to look through scalar FP_EXTEND here, but we don't need to look throug ZERO_EXTEND or SIGN_EXTEND for integer?
For integers, I think the `DAG.getSplat` would be an implicit truncation for us. But it seems that the float does not work.
https://github.com/llvm/llvm-project/pull/88615
More information about the llvm-commits
mailing list