[llvm] [RISCV][ISel] Combine scalable vector fadd/fsub/fmul with fp extend. (PR #88615)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 22:47:19 PDT 2024
================
@@ -13597,6 +13599,13 @@ struct NodeExtensionHelper {
case RISCVISD::VZEXT_VL:
case RISCVISD::FP_EXTEND_VL:
return OrigOperand.getOperand(0);
+ case ISD::SPLAT_VECTOR: {
+ SDValue Op = OrigOperand.getOperand(0);
+ if (Op.getOpcode() == ISD::FP_EXTEND)
+ return Op;
----------------
sun-jacobi wrote:
> >How does this work for fixed length float splats currently if we didn't already handle RISCVISD::VFMV_V_F_VL? Since in https://github.com/llvm/llvm-project/pull/81248 it looks like we emit vfwadd.vf
> The extend on those tests are happening in the vector domain not the scalar domain I think.
Yes, you are right. We also need to handle the extension in the scalar domain (i.e. similar to #87249) for `RISCVISD::VFMV_V_F_VL`. Thanks for pointing out this.
https://github.com/llvm/llvm-project/pull/88615
More information about the llvm-commits
mailing list