[llvm] [RISCV][llvm-mca] Use Sched*MC for Zvk MC instructions and add Zvk tests for P600 (PR #89256)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 11:01:29 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/89256
>From 7ddc58fe6de02ed962c034543015ccb06421f21d Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 08:18:28 -0700
Subject: [PATCH 01/11] [RISCV] Use Sched*MC for Zvk MC instructions
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 24 ++++++++++++----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index aac7dc444a2de3..84c4ae859ef3cb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -24,11 +24,9 @@ def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
- Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
- ReadVIALUV_WorstCase, ReadVMask]>;
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
- Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase,
- ReadVIALUX_WorstCase, ReadVMask]>;
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
}
class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
@@ -57,13 +55,13 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
(ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
- Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
- ReadVMask]>;
+ SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
}
// op vd, vs2, vs1
class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
- : VALUVVNoVm<funct6, opv, opcodestr> {
+ : VALUVVNoVm<funct6, opv, opcodestr>,
+ SchedUnaryMC<"WriteVIALUI", "ReadVIALUV"> {
let Inst{6-0} = OPC_OP_VE.Value;
}
@@ -71,7 +69,8 @@ class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1),
- opcodestr, "$vd, $vs2, $vs1"> {
+ opcodestr, "$vd, $vs2, $vs1">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -79,7 +78,8 @@ class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
// op vd, vs2, imm
class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
- : VALUVINoVm<funct6, opcodestr, optype> {
+ : VALUVINoVm<funct6, opcodestr, optype>,
+ SchedUnaryMC<"WriteVIALUV", "ReadVIALUV"> {
let Inst{6-0} = OPC_OP_VE.Value;
let Inst{14-12} = OPMVV.Value;
}
@@ -88,7 +88,8 @@ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
: RVInstIVI<funct6, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, optype:$imm),
- opcodestr, "$vd, $vs2, $imm"> {
+ opcodestr, "$vd, $vs2, $imm">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -100,7 +101,8 @@ class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
string opcodestr>
: RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
- opcodestr, "$vd, $vs2"> {
+ opcodestr, "$vd, $vs2">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
>From 38d01b4f9e4fced22bfb2dbfe8a34c21b1439af1 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 16 Apr 2024 13:00:20 -0700
Subject: [PATCH 02/11] [RISCV][llvm-mca] Add Zvbb llvm-mca tests for P600
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvbb.s | 472 ++++++++++++++++++
1 file changed, 472 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
new file mode 100644
index 00000000000000..cee5c390d7c54b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
@@ -0,0 +1,472 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, mf8, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+# Show SEW does not matter
+vsetvli zero, zero, e64, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 136
+# CHECK-NEXT: Total Cycles: 182
+# CHECK-NEXT: Total uOps: 136
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.75
+# CHECK-NEXT: IPC: 0.75
+# CHECK-NEXT: Block RThroughput: 176.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 1.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 1.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 1.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 2.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 2.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 2.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 4.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 4.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 4.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 4.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 4.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 4.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 4.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 4.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 4.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 4.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 4.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 4.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 2.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 2.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 2.00 vwsll.vi v4, v8, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 176.00 176.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v4, v8, 8
>From 6d84f4dfaff761e8b5e4da45d7591b142a7cb497 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 16 Apr 2024 13:03:28 -0700
Subject: [PATCH 03/11] [RISCV][llvm-mca] Add Zvbc llvm-mca tests for P600
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvbc.s | 176 ++++++++++++++++++
1 file changed, 176 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
new file mode 100644
index 00000000000000..44278f1e3859ea
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
@@ -0,0 +1,176 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, mf8, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e32, mf4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e32, m1, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e32, m2, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e32, m4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e32, m8, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+# Show SEW does not matter
+vsetvli zero, zero, e64, m4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 40
+# CHECK-NEXT: Total Cycles: 45
+# CHECK-NEXT: Total uOps: 40
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.89
+# CHECK-NEXT: IPC: 0.89
+# CHECK-NEXT: Block RThroughput: 44.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 4.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vclmulh.vx v4, v8, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 44.00 44.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
>From b72acf2d2a1c82122f60068701e783cd85144f5d Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 08:19:00 -0700
Subject: [PATCH 04/11] [RISCV][llvm-mca] Add P600 llvm-mca tests for Zvkg
extension
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvkg.s | 128 ++++++++++++++++++
1 file changed, 128 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
new file mode 100644
index 00000000000000..21b6eb19dde7a3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
@@ -0,0 +1,128 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, mf8, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, mf4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+# Show SEW does not matter
+vsetvli zero, zero, e64, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 24
+# CHECK-NEXT: Total Cycles: 40
+# CHECK-NEXT: Total uOps: 24
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.60
+# CHECK-NEXT: Block RThroughput: 36.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vgmul.vv v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 36.00 36.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vgmul.vv v4, v8
>From 59056148eb6ca2ed1f81f6f96593c66934afb9b3 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 08:22:45 -0700
Subject: [PATCH 05/11] [RISCV][llvm-mca] Add P600 llvm-mca tests for Zvned
extension
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvkned.s | 296 ++++++++++++++++++
1 file changed, 296 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
new file mode 100644
index 00000000000000..6e555914c038cf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
@@ -0,0 +1,296 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e64, mf8, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e64, mf4, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e64, mf2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+# Show SEW does not matter
+vsetvli zero, zero, e16, m4, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 80
+# CHECK-NEXT: Total Cycles: 164
+# CHECK-NEXT: Total uOps: 80
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.49
+# CHECK-NEXT: IPC: 0.49
+# CHECK-NEXT: Block RThroughput: 162.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vaesz.vs v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 161.00 163.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesz.vs v4, v8
>From 23d639d4c16e031c81fe39cb1afd5d58294dc274 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 08:42:37 -0700
Subject: [PATCH 06/11] [RISCV][llvm-mca] Add P600 llvm-mca tests for Zvknhb
extension
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s | 229 ++++++++++++++++++
1 file changed, 229 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
new file mode 100644
index 00000000000000..b69cb13adb67a3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
@@ -0,0 +1,229 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, mf8, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, mf4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, mf8, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, mf4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, mf2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m8, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 56
+# CHECK-NEXT: Total Cycles: 100
+# CHECK-NEXT: Total uOps: 56
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.56
+# CHECK-NEXT: IPC: 0.56
+# CHECK-NEXT: Block RThroughput: 96.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v4, v8, v12
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 14.00 - - - - - - 98.00 94.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v4, v8, v12
>From a71f103c7e68a8605ddd72519127cff2a402e7f6 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 08:45:39 -0700
Subject: [PATCH 07/11] [RISCV][llvm-mca] Add P600 llvm-mca tests for Zvksed
extension
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvksed.s | 152 ++++++++++++++++++
1 file changed, 152 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
new file mode 100644
index 00000000000000..3f8d4d4cf51e5b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e64, mf8, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, mf4, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+# Show SEW does not matter
+vsetvli zero, zero, e16, m4, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 32
+# CHECK-NEXT: Total Cycles: 56
+# CHECK-NEXT: Total uOps: 32
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.57
+# CHECK-NEXT: IPC: 0.57
+# CHECK-NEXT: Block RThroughput: 54.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vsm4r.vs v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 53.00 55.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm4r.vs v4, v8
>From 88ad20e91db3e9278e19551eea3b77ffaef14349 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 08:50:37 -0700
Subject: [PATCH 08/11] [RISCV][llvm-mca] Add P600 llvm-mca tests for Zvksh
extension
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvksh.s | 128 ++++++++++++++++++
1 file changed, 128 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
new file mode 100644
index 00000000000000..783dc21bc5847b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
@@ -0,0 +1,128 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e64, mf8, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf4, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+# Show SEW does not matter
+vsetvli zero, zero, e16, m4, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 24
+# CHECK-NEXT: Total Cycles: 38
+# CHECK-NEXT: Total uOps: 24
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.63
+# CHECK-NEXT: IPC: 0.63
+# CHECK-NEXT: Block RThroughput: 36.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsm3c.vi v4, v8, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 36.00 36.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm3c.vi v4, v8, 8
>From a2c40c789bf7789cf206a960a5535945e88453c9 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 10:04:18 -0700
Subject: [PATCH 09/11] fixup! move sched definitions
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 84c4ae859ef3cb..53d442cbd8db65 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -60,8 +60,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
// op vd, vs2, vs1
class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
- : VALUVVNoVm<funct6, opv, opcodestr>,
- SchedUnaryMC<"WriteVIALUI", "ReadVIALUV"> {
+ : VALUVVNoVm<funct6, opv, opcodestr> {
let Inst{6-0} = OPC_OP_VE.Value;
}
@@ -70,7 +69,7 @@ class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1),
opcodestr, "$vd, $vs2, $vs1">,
- SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", "ReadVIALUV"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -78,8 +77,7 @@ class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
// op vd, vs2, imm
class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
- : VALUVINoVm<funct6, opcodestr, optype>,
- SchedUnaryMC<"WriteVIALUV", "ReadVIALUV"> {
+ : VALUVINoVm<funct6, opcodestr, optype> {
let Inst{6-0} = OPC_OP_VE.Value;
let Inst{14-12} = OPMVV.Value;
}
@@ -159,7 +157,8 @@ let Predicates = [HasStdExtZvkned] in {
defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
- def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>;
+ def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
+ SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>;
let RVVConstraint = VS2Constraint in
def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">;
@@ -167,13 +166,15 @@ let Predicates = [HasStdExtZvkned] in {
let Predicates = [HasStdExtZvksed] in {
let RVVConstraint = NoConstraint in
- def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>;
+ def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
+ SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
} // Predicates = [HasStdExtZvksed]
let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>;
- def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
+ def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
+ SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
} // Predicates = [HasStdExtZvksh]
//===----------------------------------------------------------------------===//
>From b6ae5129b1c0c37739e09fd213f9f853de3b0dbe Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 10:16:49 -0700
Subject: [PATCH 10/11] fixup! move Sched*MC for PALUVVNoVmTernary and
PALUVINoVmBinary
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 28 ++++++++++++++--------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 53d442cbd8db65..3b749bfbb6ae8e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -68,8 +68,7 @@ class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1),
- opcodestr, "$vd, $vs2, $vs1">,
- SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", "ReadVIALUV"> {
+ opcodestr, "$vd, $vs2, $vs1"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -86,8 +85,7 @@ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
: RVInstIVI<funct6, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, optype:$imm),
- opcodestr, "$vd, $vs2, $imm">,
- SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
+ opcodestr, "$vd, $vs2, $imm"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -142,14 +140,22 @@ let Predicates = [HasStdExtZvkb] in {
} // Predicates = [HasStdExtZvkb]
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
- def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">;
+ def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">;
} // Predicates = [HasStdExtZvkg]
let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {
- def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">;
- def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">;
- def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">;
+ def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
+ def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
+ def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
} // Predicates = [HasStdExtZvknhaOrZvknhb]
let Predicates = [HasStdExtZvkned] in {
@@ -159,7 +165,8 @@ let Predicates = [HasStdExtZvkned] in {
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
- def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>;
+ def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
let RVVConstraint = VS2Constraint in
def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">;
} // Predicates = [HasStdExtZvkned]
@@ -172,7 +179,8 @@ let Predicates = [HasStdExtZvksed] in {
} // Predicates = [HasStdExtZvksed]
let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
- def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>;
+ def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
} // Predicates = [HasStdExtZvksh]
>From 040f9ec247f533456cedaa0afcb61dc2512b9295 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 18 Apr 2024 11:01:08 -0700
Subject: [PATCH 11/11] fixup! fix test cases
---
.../tools/llvm-mca/RISCV/SiFiveP600/zvbb.s | 187 +++++++++---------
.../tools/llvm-mca/RISCV/SiFiveP600/zvbc.s | 103 ++--------
.../tools/llvm-mca/RISCV/SiFiveP600/zvkned.s | 138 +++----------
.../tools/llvm-mca/RISCV/SiFiveP600/zvksed.s | 54 +----
.../tools/llvm-mca/RISCV/SiFiveP600/zvksh.s | 45 +----
5 files changed, 147 insertions(+), 380 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
index cee5c390d7c54b..4207477d0e7ae2 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-vsetvli zero, zero, e32, mf8, tu, mu
+vsetvli zero, zero, e8, mf8, tu, mu
vandn.vv v4, v8, v12
vandn.vx v4, v8, a0
vbrev.v v4, v8
@@ -20,7 +20,7 @@ vwsll.vv v4, v8, v12
vwsll.vx v4, v8, a0
vwsll.vi v4, v8, 8
-vsetvli zero, zero, e32, mf4, tu, mu
+vsetvli zero, zero, e16, mf4, tu, mu
vandn.vv v4, v8, v12
vandn.vx v4, v8, a0
vbrev.v v4, v8
@@ -111,58 +111,53 @@ vror.vv v4, v8, v12
vror.vx v4, v8, a0
vror.vi v4, v8, 8
-vwsll.vv v4, v8, v12
-vwsll.vx v4, v8, a0
-vwsll.vi v4, v8, 8
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
vsetvli zero, zero, e32, m8, tu, mu
-vandn.vv v4, v8, v12
-vandn.vx v4, v8, a0
-vbrev.v v4, v8
-vbrev8.v v4, v8
-vrev8.v v4, v8
-vclz.v v4, v8
-vctz.v v4, v8
-vcpop.v v4, v8
-vrol.vv v4, v8, v12
-vrol.vx v4, v8, a0
-vror.vv v4, v8, v12
-vror.vx v4, v8, a0
-vror.vi v4, v8, 8
-
-vwsll.vv v4, v8, v12
-vwsll.vx v4, v8, a0
-vwsll.vi v4, v8, 8
+vandn.vv v8, v16, v24
+vandn.vx v8, v16, a0
+vbrev.v v8, v16
+vbrev8.v v8, v16
+vrev8.v v8, v16
+vclz.v v8, v16
+vctz.v v8, v16
+vcpop.v v8, v16
+vrol.vv v8, v16, v24
+vrol.vx v8, v16, a0
+vror.vv v8, v16, v24
+vror.vx v8, v16, a0
+vror.vi v8, v16, 8
# Show SEW does not matter
-vsetvli zero, zero, e64, m4, tu, mu
+vsetvli zero, zero, e16, m4, tu, mu
vandn.vv v4, v8, v12
vandn.vx v4, v8, a0
-vbrev.v v4, v8
+vbrev.v v4, v8
vbrev8.v v4, v8
-vrev8.v v4, v8
-vclz.v v4, v8
-vctz.v v4, v8
-vcpop.v v4, v8
-vrol.vv v4, v8, v12
-vrol.vx v4, v8, a0
-vror.vv v4, v8, v12
-vror.vx v4, v8, a0
-vror.vi v4, v8, 8
-
-vwsll.vv v4, v8, v12
-vwsll.vx v4, v8, a0
-vwsll.vi v4, v8, 8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 136
-# CHECK-NEXT: Total Cycles: 182
-# CHECK-NEXT: Total uOps: 136
+# CHECK-NEXT: Instructions: 133
+# CHECK-NEXT: Total Cycles: 170
+# CHECK-NEXT: Total uOps: 133
# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.75
-# CHECK-NEXT: Block RThroughput: 176.0
+# CHECK-NEXT: uOps Per Cycle: 0.78
+# CHECK-NEXT: IPC: 0.78
+# CHECK-NEXT: Block RThroughput: 164.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -173,7 +168,7 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
@@ -190,7 +185,7 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
@@ -272,27 +267,24 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: 1 1 2.00 vror.vv v4, v8, v12
# CHECK-NEXT: 1 1 2.00 vror.vx v4, v8, a0
# CHECK-NEXT: 1 1 2.00 vror.vi v4, v8, 8
-# CHECK-NEXT: 1 6 2.00 vwsll.vv v4, v8, v12
-# CHECK-NEXT: 1 6 2.00 vwsll.vx v4, v8, a0
-# CHECK-NEXT: 1 6 2.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 6 2.00 vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 6 2.00 vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 6 2.00 vwsll.vi v8, v4, 8
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 1 4.00 vandn.vv v4, v8, v12
-# CHECK-NEXT: 1 1 4.00 vandn.vx v4, v8, a0
-# CHECK-NEXT: 1 1 4.00 vbrev.v v4, v8
-# CHECK-NEXT: 1 1 4.00 vbrev8.v v4, v8
-# CHECK-NEXT: 1 1 4.00 vrev8.v v4, v8
-# CHECK-NEXT: 1 1 4.00 vclz.v v4, v8
-# CHECK-NEXT: 1 1 4.00 vctz.v v4, v8
-# CHECK-NEXT: 1 1 4.00 vcpop.v v4, v8
-# CHECK-NEXT: 1 1 4.00 vrol.vv v4, v8, v12
-# CHECK-NEXT: 1 1 4.00 vrol.vx v4, v8, a0
-# CHECK-NEXT: 1 1 4.00 vror.vv v4, v8, v12
-# CHECK-NEXT: 1 1 4.00 vror.vx v4, v8, a0
-# CHECK-NEXT: 1 1 4.00 vror.vi v4, v8, 8
-# CHECK-NEXT: 1 6 4.00 vwsll.vv v4, v8, v12
-# CHECK-NEXT: 1 6 4.00 vwsll.vx v4, v8, a0
-# CHECK-NEXT: 1 6 4.00 vwsll.vi v4, v8, 8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vandn.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vandn.vx v8, v16, a0
+# CHECK-NEXT: 1 1 4.00 vbrev.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vbrev8.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vrev8.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vclz.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vctz.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vcpop.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vrol.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vrol.vx v8, v16, a0
+# CHECK-NEXT: 1 1 4.00 vror.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vror.vx v8, v16, a0
+# CHECK-NEXT: 1 1 4.00 vror.vi v8, v16, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
# CHECK-NEXT: 1 1 2.00 vandn.vv v4, v8, v12
# CHECK-NEXT: 1 1 2.00 vandn.vx v4, v8, a0
# CHECK-NEXT: 1 1 2.00 vbrev.v v4, v8
@@ -306,9 +298,9 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: 1 1 2.00 vror.vv v4, v8, v12
# CHECK-NEXT: 1 1 2.00 vror.vx v4, v8, a0
# CHECK-NEXT: 1 1 2.00 vror.vi v4, v8, 8
-# CHECK-NEXT: 1 6 2.00 vwsll.vv v4, v8, v12
-# CHECK-NEXT: 1 6 2.00 vwsll.vx v4, v8, a0
-# CHECK-NEXT: 1 6 2.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 6 2.00 vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 6 2.00 vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 6 2.00 vwsll.vi v8, v4, 8
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
@@ -330,11 +322,11 @@ vwsll.vi v4, v8, 8
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 8.00 - - - - - - 176.00 176.00 - - -
+# CHECK-NEXT: - - - - 8.00 - - - - - - 164.00 164.00 - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
@@ -351,7 +343,7 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
@@ -430,31 +422,28 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vcpop.v v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vrol.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v8, v4, 8
# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vandn.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vandn.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vbrev.v v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vbrev8.v v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vrev8.v v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclz.v v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vctz.v v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vcpop.v v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vrol.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vrol.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vror.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vwsll.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vwsll.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vwsll.vi v4, v8, 8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vandn.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vandn.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vbrev.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vbrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vctz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vcpop.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vrol.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vrol.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vror.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vi v8, v16, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vbrev.v v4, v8
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vbrev8.v v4, v8
@@ -464,9 +453,9 @@ vwsll.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vcpop.v v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vrol.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v8, v4, 8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
index 44278f1e3859ea..4ea60a47ad30da 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
@@ -1,64 +1,41 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-vsetvli zero, zero, e32, mf8, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
+# These instructions only work with e64
-vsetvli zero, zero, e32, mf4, tu, mu
+vsetvli zero, zero, e64, m1, tu, mu
vclmul.vv v4, v8, v12
vclmul.vx v4, v8, a0
vclmulh.vv v4, v8, v12
vclmulh.vx v4, v8, a0
-vsetvli zero, zero, e32, mf2, tu, mu
+vsetvli zero, zero, e64, m2, tu, mu
vclmul.vv v4, v8, v12
vclmul.vx v4, v8, a0
vclmulh.vv v4, v8, v12
vclmulh.vx v4, v8, a0
-vsetvli zero, zero, e32, m1, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e32, m2, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e32, m4, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e32, m8, tu, mu
+vsetvli zero, zero, e64, m4, tu, mu
vclmul.vv v4, v8, v12
vclmul.vx v4, v8, a0
vclmulh.vv v4, v8, v12
vclmulh.vx v4, v8, a0
-# Show SEW does not matter
-vsetvli zero, zero, e64, m4, tu, mu
+vsetvli zero, zero, e64, m8, tu, mu
vclmul.vv v4, v8, v12
vclmul.vx v4, v8, a0
vclmulh.vv v4, v8, v12
vclmulh.vx v4, v8, a0
# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 40
-# CHECK-NEXT: Total Cycles: 45
-# CHECK-NEXT: Total uOps: 40
+# CHECK-NEXT: Instructions: 20
+# CHECK-NEXT: Total Cycles: 27
+# CHECK-NEXT: Total uOps: 20
# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.89
-# CHECK-NEXT: IPC: 0.89
-# CHECK-NEXT: Block RThroughput: 44.0
+# CHECK-NEXT: uOps Per Cycle: 0.74
+# CHECK-NEXT: IPC: 0.74
+# CHECK-NEXT: Block RThroughput: 30.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -69,46 +46,26 @@ vclmulh.vx v4, v8, a0
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 1 1.00 vclmul.vv v4, v8, v12
# CHECK-NEXT: 1 1 1.00 vclmul.vx v4, v8, a0
# CHECK-NEXT: 1 1 1.00 vclmulh.vv v4, v8, v12
# CHECK-NEXT: 1 1 1.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 1 2.00 vclmul.vv v4, v8, v12
# CHECK-NEXT: 1 1 2.00 vclmul.vx v4, v8, a0
# CHECK-NEXT: 1 1 2.00 vclmulh.vv v4, v8, v12
# CHECK-NEXT: 1 1 2.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 1 4.00 vclmul.vv v4, v8, v12
# CHECK-NEXT: 1 1 4.00 vclmul.vx v4, v8, a0
# CHECK-NEXT: 1 1 4.00 vclmulh.vv v4, v8, v12
# CHECK-NEXT: 1 1 4.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 1 2.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 1 2.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 1 2.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 1 2.00 vclmulh.vx v4, v8, a0
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
@@ -130,47 +87,27 @@ vclmulh.vx v4, v8, a0
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 8.00 - - - - - - 44.00 44.00 - - -
+# CHECK-NEXT: - - - - 4.00 - - - - - - 30.00 30.00 - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclmul.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vx v4, v8, a0
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclmulh.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
index 6e555914c038cf..f1c61c6f447f91 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
@@ -1,40 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-vsetvli zero, zero, e64, mf8, tu, mu
-vaesef.vv v4, v8
-vaesef.vs v4, v8
-vaesem.vv v4, v8
-vaesem.vs v4, v8
-vaesdm.vv v4, v8
-vaesdm.vs v4, v8
-vaeskf1.vi v4, v8, 8
-vaeskf2.vi v4, v8, 8
-vaesz.vs v4, v8
-
-vsetvli zero, zero, e64, mf4, tu, mu
-vaesef.vv v4, v8
-vaesef.vs v4, v8
-vaesem.vv v4, v8
-vaesem.vs v4, v8
-vaesdm.vv v4, v8
-vaesdm.vs v4, v8
-vaeskf1.vi v4, v8, 8
-vaeskf2.vi v4, v8, 8
-vaesz.vs v4, v8
-
-vsetvli zero, zero, e64, mf2, tu, mu
-vaesef.vv v4, v8
-vaesef.vs v4, v8
-vaesem.vv v4, v8
-vaesem.vs v4, v8
-vaesdm.vv v4, v8
-vaesdm.vs v4, v8
-vaeskf1.vi v4, v8, 8
-vaeskf2.vi v4, v8, 8
-vaesz.vs v4, v8
+# These instructions only support e32
-vsetvli zero, zero, e64, m1, tu, mu
+vsetvli zero, zero, e32, mf2, tu, mu
vaesef.vv v4, v8
vaesef.vs v4, v8
vaesem.vv v4, v8
@@ -45,7 +14,7 @@ vaeskf1.vi v4, v8, 8
vaeskf2.vi v4, v8, 8
vaesz.vs v4, v8
-vsetvli zero, zero, e64, m2, tu, mu
+vsetvli zero, zero, e32, m1, tu, mu
vaesef.vv v4, v8
vaesef.vs v4, v8
vaesem.vv v4, v8
@@ -56,7 +25,7 @@ vaeskf1.vi v4, v8, 8
vaeskf2.vi v4, v8, 8
vaesz.vs v4, v8
-vsetvli zero, zero, e64, m4, tu, mu
+vsetvli zero, zero, e32, m2, tu, mu
vaesef.vv v4, v8
vaesef.vs v4, v8
vaesem.vv v4, v8
@@ -67,7 +36,7 @@ vaeskf1.vi v4, v8, 8
vaeskf2.vi v4, v8, 8
vaesz.vs v4, v8
-vsetvli zero, zero, e64, m8, tu, mu
+vsetvli zero, zero, e32, m4, tu, mu
vaesef.vv v4, v8
vaesef.vs v4, v8
vaesem.vv v4, v8
@@ -78,8 +47,7 @@ vaeskf1.vi v4, v8, 8
vaeskf2.vi v4, v8, 8
vaesz.vs v4, v8
-# Show SEW does not matter
-vsetvli zero, zero, e16, m4, tu, mu
+vsetvli zero, zero, e32, m8, tu, mu
vaesef.vv v4, v8
vaesef.vs v4, v8
vaesem.vv v4, v8
@@ -91,14 +59,14 @@ vaeskf2.vi v4, v8, 8
vaesz.vs v4, v8
# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 80
-# CHECK-NEXT: Total Cycles: 164
-# CHECK-NEXT: Total uOps: 80
+# CHECK-NEXT: Instructions: 50
+# CHECK-NEXT: Total Cycles: 72
+# CHECK-NEXT: Total uOps: 50
# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.49
-# CHECK-NEXT: IPC: 0.49
-# CHECK-NEXT: Block RThroughput: 162.0
+# CHECK-NEXT: uOps Per Cycle: 0.69
+# CHECK-NEXT: IPC: 0.69
+# CHECK-NEXT: Block RThroughput: 72.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -109,27 +77,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 1 4.00 vaesef.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesef.vs v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesem.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesem.vs v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesdm.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesdm.vs v4, v8
-# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v4, v8, 8
-# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v4, v8, 8
-# CHECK-NEXT: 1 1 4.00 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 1 4.00 vaesef.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesef.vs v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesem.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesem.vs v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesdm.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vaesdm.vs v4, v8
-# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v4, v8, 8
-# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v4, v8, 8
-# CHECK-NEXT: 1 1 4.00 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 1 0.50 vaesef.vv v4, v8
# CHECK-NEXT: 1 1 0.50 vaesef.vs v4, v8
# CHECK-NEXT: 1 1 0.50 vaesem.vv v4, v8
@@ -139,7 +87,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: 1 1 0.50 vaeskf1.vi v4, v8, 8
# CHECK-NEXT: 1 1 0.50 vaeskf2.vi v4, v8, 8
# CHECK-NEXT: 1 1 0.50 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 1 0.50 vaesef.vv v4, v8
# CHECK-NEXT: 1 1 0.50 vaesef.vs v4, v8
# CHECK-NEXT: 1 1 0.50 vaesem.vv v4, v8
@@ -149,7 +97,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: 1 1 0.50 vaeskf1.vi v4, v8, 8
# CHECK-NEXT: 1 1 0.50 vaeskf2.vi v4, v8, 8
# CHECK-NEXT: 1 1 0.50 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: 1 1 1.00 vaesef.vv v4, v8
# CHECK-NEXT: 1 1 1.00 vaesef.vs v4, v8
# CHECK-NEXT: 1 1 1.00 vaesem.vv v4, v8
@@ -159,7 +107,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: 1 1 1.00 vaeskf1.vi v4, v8, 8
# CHECK-NEXT: 1 1 1.00 vaeskf2.vi v4, v8, 8
# CHECK-NEXT: 1 1 1.00 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 1 2.00 vaesef.vv v4, v8
# CHECK-NEXT: 1 1 2.00 vaesef.vs v4, v8
# CHECK-NEXT: 1 1 2.00 vaesem.vv v4, v8
@@ -169,7 +117,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: 1 1 2.00 vaeskf1.vi v4, v8, 8
# CHECK-NEXT: 1 1 2.00 vaeskf2.vi v4, v8, 8
# CHECK-NEXT: 1 1 2.00 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 1 4.00 vaesef.vv v4, v8
# CHECK-NEXT: 1 1 4.00 vaesef.vs v4, v8
# CHECK-NEXT: 1 1 4.00 vaesem.vv v4, v8
@@ -179,16 +127,6 @@ vaesz.vs v4, v8
# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v4, v8, 8
# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v4, v8, 8
# CHECK-NEXT: 1 1 4.00 vaesz.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 2.00 vaesef.vv v4, v8
-# CHECK-NEXT: 1 1 2.00 vaesef.vs v4, v8
-# CHECK-NEXT: 1 1 2.00 vaesem.vv v4, v8
-# CHECK-NEXT: 1 1 2.00 vaesem.vs v4, v8
-# CHECK-NEXT: 1 1 2.00 vaesdm.vv v4, v8
-# CHECK-NEXT: 1 1 2.00 vaesdm.vs v4, v8
-# CHECK-NEXT: 1 1 2.00 vaeskf1.vi v4, v8, 8
-# CHECK-NEXT: 1 1 2.00 vaeskf2.vi v4, v8, 8
-# CHECK-NEXT: 1 1 2.00 vaesz.vs v4, v8
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
@@ -210,31 +148,11 @@ vaesz.vs v4, v8
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 8.00 - - - - - - 161.00 163.00 - - -
+# CHECK-NEXT: - - - - 5.00 - - - - - - 69.00 75.00 - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf1.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesem.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf1.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesef.vv v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesef.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vv v4, v8
@@ -244,7 +162,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf1.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf2.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesef.vv v4, v8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesef.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesem.vv v4, v8
@@ -254,7 +172,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf1.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf2.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesef.vv v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesef.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesem.vv v4, v8
@@ -264,7 +182,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaeskf1.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaeskf2.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vv v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesef.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesem.vv v4, v8
@@ -274,7 +192,7 @@ vaesz.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaeskf1.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaeskf2.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vv v4, v8
# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vv v4, v8
@@ -284,13 +202,3 @@ vaesz.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaeskf1.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesz.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesem.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesem.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesdm.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesdm.vs v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaeskf1.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaeskf2.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesz.vs v4, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
index 3f8d4d4cf51e5b..96795658508bc0 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
@@ -1,15 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-vsetvli zero, zero, e64, mf8, tu, mu
-vsm4k.vi v4, v8, 8
-vsm4r.vv v4, v8
-vsm4r.vs v4, v8
-
-vsetvli zero, zero, e32, mf4, tu, mu
-vsm4k.vi v4, v8, 8
-vsm4r.vv v4, v8
-vsm4r.vs v4, v8
+# These instructions only support e32
vsetvli zero, zero, e32, mf2, tu, mu
vsm4k.vi v4, v8, 8
@@ -36,21 +28,15 @@ vsm4k.vi v4, v8, 8
vsm4r.vv v4, v8
vsm4r.vs v4, v8
-# Show SEW does not matter
-vsetvli zero, zero, e16, m4, tu, mu
-vsm4k.vi v4, v8, 8
-vsm4r.vv v4, v8
-vsm4r.vs v4, v8
-
# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 32
-# CHECK-NEXT: Total Cycles: 56
-# CHECK-NEXT: Total uOps: 32
+# CHECK-NEXT: Instructions: 20
+# CHECK-NEXT: Total Cycles: 24
+# CHECK-NEXT: Total uOps: 20
# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.57
-# CHECK-NEXT: IPC: 0.57
-# CHECK-NEXT: Block RThroughput: 54.0
+# CHECK-NEXT: uOps Per Cycle: 0.83
+# CHECK-NEXT: IPC: 0.83
+# CHECK-NEXT: Block RThroughput: 24.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -61,14 +47,6 @@ vsm4r.vs v4, v8
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 1 4.00 vsm4k.vi v4, v8, 8
-# CHECK-NEXT: 1 1 4.00 vsm4r.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vsm4r.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 1 4.00 vsm4k.vi v4, v8, 8
-# CHECK-NEXT: 1 1 4.00 vsm4r.vv v4, v8
-# CHECK-NEXT: 1 1 4.00 vsm4r.vs v4, v8
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 1 0.50 vsm4k.vi v4, v8, 8
# CHECK-NEXT: 1 1 0.50 vsm4r.vv v4, v8
@@ -89,10 +67,6 @@ vsm4r.vs v4, v8
# CHECK-NEXT: 1 1 4.00 vsm4k.vi v4, v8, 8
# CHECK-NEXT: 1 1 4.00 vsm4r.vv v4, v8
# CHECK-NEXT: 1 1 4.00 vsm4r.vs v4, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 2.00 vsm4k.vi v4, v8, 8
-# CHECK-NEXT: 1 1 2.00 vsm4r.vv v4, v8
-# CHECK-NEXT: 1 1 2.00 vsm4r.vs v4, v8
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
@@ -114,18 +88,10 @@ vsm4r.vs v4, v8
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 8.00 - - - - - - 53.00 55.00 - - -
+# CHECK-NEXT: - - - - 5.00 - - - - - - 21.00 27.00 - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4k.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4k.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vs v4, v8
# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8
@@ -146,7 +112,3 @@ vsm4r.vs v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4k.vi v4, v8, 8
# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vv v4, v8
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vs v4, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4k.vi v4, v8, 8
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4r.vv v4, v8
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm4r.vs v4, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
index 783dc21bc5847b..7dba25a3cc1033 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
@@ -1,13 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-vsetvli zero, zero, e64, mf8, tu, mu
-vsm3me.vv v4, v8, v12
-vsm3c.vi v4, v8, 8
-
-vsetvli zero, zero, e32, mf4, tu, mu
-vsm3me.vv v4, v8, v12
-vsm3c.vi v4, v8, 8
+# These instructions only support e32
vsetvli zero, zero, e32, mf2, tu, mu
vsm3me.vv v4, v8, v12
@@ -29,20 +23,15 @@ vsetvli zero, zero, e32, m8, tu, mu
vsm3me.vv v4, v8, v12
vsm3c.vi v4, v8, 8
-# Show SEW does not matter
-vsetvli zero, zero, e16, m4, tu, mu
-vsm3me.vv v4, v8, v12
-vsm3c.vi v4, v8, 8
-
# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 24
-# CHECK-NEXT: Total Cycles: 38
-# CHECK-NEXT: Total uOps: 24
+# CHECK-NEXT: Instructions: 15
+# CHECK-NEXT: Total Cycles: 14
+# CHECK-NEXT: Total uOps: 15
# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.63
-# CHECK-NEXT: IPC: 0.63
-# CHECK-NEXT: Block RThroughput: 36.0
+# CHECK-NEXT: uOps Per Cycle: 1.07
+# CHECK-NEXT: IPC: 1.07
+# CHECK-NEXT: Block RThroughput: 16.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -53,12 +42,6 @@ vsm3c.vi v4, v8, 8
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 1 4.00 vsm3me.vv v4, v8, v12
-# CHECK-NEXT: 1 1 4.00 vsm3c.vi v4, v8, 8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 1 4.00 vsm3me.vv v4, v8, v12
-# CHECK-NEXT: 1 1 4.00 vsm3c.vi v4, v8, 8
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 1 0.50 vsm3me.vv v4, v8, v12
# CHECK-NEXT: 1 1 0.50 vsm3c.vi v4, v8, 8
@@ -74,9 +57,6 @@ vsm3c.vi v4, v8, 8
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 1 4.00 vsm3me.vv v4, v8, v12
# CHECK-NEXT: 1 1 4.00 vsm3c.vi v4, v8, 8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 2.00 vsm3me.vv v4, v8, v12
-# CHECK-NEXT: 1 1 2.00 vsm3c.vi v4, v8, 8
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
@@ -98,16 +78,10 @@ vsm3c.vi v4, v8, 8
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 8.00 - - - - - - 36.00 36.00 - - -
+# CHECK-NEXT: - - - - 5.00 - - - - - - 16.00 16.00 - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v4, v8, 8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v4, v8, 8
# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
@@ -123,6 +97,3 @@ vsm3c.vi v4, v8, 8
# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v4, v8, v12
# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v4, v8, 8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm3me.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm3c.vi v4, v8, 8
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