[llvm] [LLVM][CodeGen][AArch64] Simplify lowering for predicate inserts. (PR #89072)

[Paul Walker via llvm-commits]

https://github.com/paulwalker-arm created https://github.com/llvm/llvm-project/pull/89072

The original code has an invalid use of UZP1 because the result vector type does not match its input vector types. Rather than insert extra nop casts I figure it would be better to use CONCAT_VECTORS because that's the operation we're performing.

NOTE: This is a step to enable more asserts in verifyTargetSDNode.

>From c2146808d989f89053d321b5c4637b5c14b8886e Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Wed, 17 Apr 2024 12:36:08 +0000
Subject: [PATCH] [LLVM][CodeGen][AArch64] Simplify lowering for predicate
 inserts.

The original code has an invalid use of UZP1 because the result
vector type does not match its input vector types. Rather than
insert extra nop casts I figure it would be better to use
CONCAT_VECTORS because that's the operation we're performing.

NOTE: This is a step to enable more asserts in verifyTargetSDNode.
---
 .../lib/Target/AArch64/AArch64ISelLowering.cpp | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index eee67a0f823c19..67f341adc598ff 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13896,16 +13896,14 @@ SDValue AArch64TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
                        DAG.getVectorIdxConstant(0, DL));
       Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0,
                        DAG.getVectorIdxConstant(NumElts / 2, DL));
-      if (Idx < (NumElts / 2)) {
-        SDValue NewLo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1,
-                                    DAG.getVectorIdxConstant(Idx, DL));
-        return DAG.getNode(AArch64ISD::UZP1, DL, VT, NewLo, Hi);
-      } else {
-        SDValue NewHi =
-            DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1,
-                        DAG.getVectorIdxConstant(Idx - (NumElts / 2), DL));
-        return DAG.getNode(AArch64ISD::UZP1, DL, VT, Lo, NewHi);
-      }
+      if (Idx < (NumElts / 2))
+        Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1,
+                         DAG.getVectorIdxConstant(Idx, DL));
+      else
+        Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1,
+                         DAG.getVectorIdxConstant(Idx - (NumElts / 2), DL));
+
+      return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
     }
 
     // Ensure the subvector is half the size of the main vector.