[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michael Maitland via llvm-commits]

================
@@ -307,44 +307,68 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX
+        : VPseudoVC_X<OpClass, RS1Class>,
+          Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
----------------
michaelmaitland wrote:

Oops, @topperc pointed out I am wrong:

> SchedRead is only used to lookup if the latency should be adjusted using a ReadAdvance. The dependency graph is defined by the register operands is tells the scheduler which instructions an instruction reads from

As a result, I think this PR is okay without having SchedRead. We can add in a follow up PR if it becomes important.

https://github.com/llvm/llvm-project/pull/86093