[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michael Maitland via llvm-commits]

================
@@ -307,44 +307,68 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX
+        : VPseudoVC_X<OpClass, RS1Class>,
+          Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
----------------
michaelmaitland wrote:

As written, this code specifies scheduling information such that each VCIX instruction writes data but does not read data. That means that if a VCIX instruction reads data in reality (which it likely does, but correct me if I am wrong), then the scheduler will not check to see if the data it reads is ready based on the write latency entry.

For example:
```
a = op b
c = vcix a
```

If there is a SchedRead for `vcix` then the scheduler will check to see what the write latency on `a` was and use that information in determining when `vcix` should be scheduled.

https://github.com/llvm/llvm-project/pull/86093