[llvm] 0822780 - [LoongArch] Fix incorrect logic in isLegalAddressingMode() (#88694)

[via llvm-commits]

Author: wanglei
Date: 2024-04-15T18:01:09+08:00
New Revision: 0822780b7ffa552b351364be350a997a47f22250

URL: https://github.com/llvm/llvm-project/commit/0822780b7ffa552b351364be350a997a47f22250
DIFF: https://github.com/llvm/llvm-project/commit/0822780b7ffa552b351364be350a997a47f22250.diff

LOG: [LoongArch] Fix incorrect logic in isLegalAddressingMode() (#88694)

This will adress issue:
https://github.com/ClangBuiltLinux/linux/issues/2014

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    llvm/test/CodeGen/LoongArch/gep-imm.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index c13b10a320f836..285d5c2a63b2da 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -4876,20 +4876,19 @@ bool LoongArchTargetLowering::isLegalAddressingMode(const DataLayout &DL,
   if (AM.BaseGV)
     return false;
 
-  // Require a 12 or 14 bit signed offset.
-  if (!isInt<12>(AM.BaseOffs) || !isShiftedInt<14, 2>(AM.BaseOffs))
+  // Require a 12-bit signed offset or 14-bit signed offset left-shifted by 2
+  // with `UAL` feature.
+  if (!isInt<12>(AM.BaseOffs) &&
+      !(isShiftedInt<14, 2>(AM.BaseOffs) && Subtarget.hasUAL()))
     return false;
 
   switch (AM.Scale) {
   case 0:
-    // "i" is not allowed.
-    if (!AM.HasBaseReg)
-      return false;
-    // Otherwise we have "r+i".
+    // "r+i" or just "i", depending on HasBaseReg.
     break;
   case 1:
     // "r+r+i" is not allowed.
-    if (AM.HasBaseReg && AM.BaseOffs != 0)
+    if (AM.HasBaseReg && AM.BaseOffs)
       return false;
     // Otherwise we have "r+r" or "r+i".
     break;
@@ -4897,7 +4896,7 @@ bool LoongArchTargetLowering::isLegalAddressingMode(const DataLayout &DL,
     // "2*r+r" or "2*r+i" is not allowed.
     if (AM.HasBaseReg || AM.BaseOffs)
       return false;
-    // Otherwise we have "r+r".
+    // Allow "2*r" as "r+r".
     break;
   default:
     return false;

diff  --git a/llvm/test/CodeGen/LoongArch/gep-imm.ll b/llvm/test/CodeGen/LoongArch/gep-imm.ll
index 52d25f9d638949..0eef7e4517f3d8 100644
--- a/llvm/test/CodeGen/LoongArch/gep-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/gep-imm.ll
@@ -4,12 +4,8 @@
 define void @test(ptr %sp, ptr %t, i32 %n) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld.d $a0, $a0, 0
 ; CHECK-NEXT:    move $a3, $zero
-; CHECK-NEXT:    ld.d $a4, $a0, 0
-; CHECK-NEXT:    lu12i.w $a0, 1
-; CHECK-NEXT:    ori $a5, $a0, 3904
-; CHECK-NEXT:    add.d $a0, $a1, $a5
-; CHECK-NEXT:    add.d $a1, $a4, $a5
 ; CHECK-NEXT:    addi.w $a2, $a2, 0
 ; CHECK-NEXT:    addi.w $a4, $a3, 0
 ; CHECK-NEXT:    bge $a4, $a2, .LBB0_2
@@ -17,10 +13,10 @@ define void @test(ptr %sp, ptr %t, i32 %n) {
 ; CHECK-NEXT:  .LBB0_1: # %while_body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    addi.d $a4, $a3, 1
-; CHECK-NEXT:    st.w $a4, $a1, 0
-; CHECK-NEXT:    st.w $a3, $a1, 4
-; CHECK-NEXT:    st.w $a4, $a0, 0
-; CHECK-NEXT:    st.w $a3, $a0, 4
+; CHECK-NEXT:    stptr.w $a4, $a0, 8000
+; CHECK-NEXT:    stptr.w $a3, $a0, 8004
+; CHECK-NEXT:    stptr.w $a4, $a1, 8000
+; CHECK-NEXT:    stptr.w $a3, $a1, 8004
 ; CHECK-NEXT:    move $a3, $a4
 ; CHECK-NEXT:    addi.w $a4, $a3, 0
 ; CHECK-NEXT:    blt $a4, $a2, .LBB0_1