[llvm] [DAG] Prevent combination on small negative value for vscale (PR #88108)

[Paul Walker via llvm-commits]

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@@ -3979,7 +3979,8 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
   // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
   if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) {
     const APInt &IntVal = N1.getConstantOperandAPInt(0);
-    return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
+    if (TLI.isPreferVScaleConst(-IntVal))
+      return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
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paulwalker-arm wrote:

Does preventing this canonicalisation improve any DAG combines or is it purely to improve instruction selection?

If it's the latter and considering we already have isel patterns for the negative imm case that emit a `SUB XRZ, CNT...`, perhaps you can just add another set of patterns that include the `add` and the emit `SUB $op, CNT`.

https://github.com/llvm/llvm-project/pull/88108