[llvm] [Spirv][HLSL] Add OpAll lowering and float vec support (PR #87952)
Nathan Gauër via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 8 07:11:21 PDT 2024
================
@@ -164,9 +178,82 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
return std::make_tuple(Res, CI, NewInstr);
}
+std::tuple<Register, ConstantFP *, bool, unsigned>
+SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
+ MachineIRBuilder *MIRBuilder,
+ MachineInstr *I,
+ const SPIRVInstrInfo *TII) {
+ const Type *LLVMFloatTy;
+ LLVMContext &Ctx = CurMF->getFunction().getContext();
+ unsigned BitWidth = 32;
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Keenuts wrote:
nit: I'd move this closer to the place where BitWidth can be read from the spvType.
https://github.com/llvm/llvm-project/pull/87952
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