[llvm] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (PR #76644)

[David Green via llvm-commits]

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@@ -24555,6 +24555,19 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
     if (auto R = foldOverflowCheck(N, DAG, /* IsAdd */ false))
       return R;
     return performFlagSettingCombine(N, DCI, AArch64ISD::SBC);
+  case AArch64ISD::BICi: {
+    KnownBits Known;
+    APInt DemandedBits =
+        APInt::getAllOnes(N->getValueType(0).getScalarSizeInBits());
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davemgreen wrote:

I would expect this not be all bits, but to only demand the bits that are not cleared by the BIC.  Again this might be difficult to test though, so it might be best to leave it as-is for the moment.

https://github.com/llvm/llvm-project/pull/76644