[llvm] [RISCV] Enable expansion mul expansion to shNadd x, (slli x, c) (PR #87105)

[Philip Reames via llvm-commits]

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@@ -551,8 +551,9 @@ define i64 @add_mul_combine_infinite_loop(i64 %x) {
 ; RV32IMB-NEXT:    sh3add a1, a1, a2
 ; RV32IMB-NEXT:    sh1add a0, a0, a0
 ; RV32IMB-NEXT:    slli a2, a0, 3
-; RV32IMB-NEXT:    addi a0, a2, 2047
-; RV32IMB-NEXT:    addi a0, a0, 1
+; RV32IMB-NEXT:    li a3, 1
+; RV32IMB-NEXT:    slli a3, a3, 11
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preames wrote:

Note that we bypass the early shift here, so this sh3add match is actually an improvement.  Note that with zbs, the immediate materialization becomes a single bseti.

https://github.com/llvm/llvm-project/pull/87105