[llvm] [RISCV] Combine (or disjoint ext, ext) -> vwadd (PR #86929)

[Luke Lau via llvm-commits]

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@@ -13675,6 +13675,7 @@ struct NodeExtensionHelper {
     case RISCVISD::ADD_VL:
     case RISCVISD::VWADD_W_VL:
     case RISCVISD::VWADDU_W_VL:
+    case ISD::OR:
       return RISCVISD::VWADD_VL;
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lukel97 wrote:

I couldn't think of a good way to add a test case that had the disjoint flag inferred, since in order for the bits to be disjoint the highest bit of the sexted operand needs to be cleared, which causes the sext to be combined to a zext. Using @llvm.assume didn't help either. I'll add a test case where we're just explicitly setting the disjoint flag though.

https://github.com/llvm/llvm-project/pull/86929