[llvm] [AArch64][GISEL] Reduce likelihood of hash collisions for mappings in RegisterBankInfo (PR #87033)

[Matt Arsenault via llvm-commits]

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@@ -221,8 +221,8 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
       if (!OperandsMapping[0]) {
         if (MI.isRegSequence()) {
           // For reg_sequence, the result size does not match the input.
-          unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),
-                                              MRI, TRI);
+          unsigned ResultSize =
+              getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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arsenm wrote:

Unrelated formatting change 

https://github.com/llvm/llvm-project/pull/87033