[llvm] [MC][AArch64] Segregate constant pool caches by size. (PR #86832)

[via llvm-commits]

AtariDreams wrote:

> LGTM
> 
> If we want to optimize on AArch64 specifically, we could teach the assembler to rewrite `ldr x0, =smallconstant` to `ldr w0, =smallconstant`. But probably not the effort.

MASM does this for x86 and I think AArch64 too. 

https://github.com/llvm/llvm-project/pull/86832