[llvm] [AArch64] Optimization of repeated constant loads (#51483) (PR #86249)

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ParkHanbum wrote:

@davemgreen Do we support the same ORR format as GCC? 
I get an error when I give ORR three registers as Operand, I wonder if this is because it doesn't support Instruction Format.
https://gcc.godbolt.org/z/131YsEY6W

could you little advise which instruction can I use please?


https://github.com/llvm/llvm-project/pull/86249