[llvm] [AArch64] Optimization of repeated constant loads (#51483) (PR #86249)

[via llvm-commits]

ParkHanbum wrote:

@davemgreen Do we support the same ORR format as GCC? 
I get an error when I give ORR three registers as Operand, I wonder if this is because it doesn't support Instruction Format.
https://gcc.godbolt.org/z/131YsEY6W

```
def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
                                          logical_imm32:$imm), 0>;
def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
                                          logical_imm64:$imm), 0>;
```

if I need to add new instruction format, let me know! 


https://github.com/llvm/llvm-project/pull/86249