[llvm] [Target][RISCV] Add HwMode support to subregister index size/offset. (PR #86368)

[Björn Pettersson via llvm-commits]

bjope wrote:

I guess the RISCV definitions can be seen as serving as an example. But I don't see any test case that actually verify that we get different size/offset depending on HwMode. I.e. that TargetRegisterInfo::getSubRegIdxSize and TargetRegisterInfo::getSubRegIdxOffset really would find the expected entries in the tables. But I'm not quite sure what kind of test that can be used to demonstrate that behavior.

https://github.com/llvm/llvm-project/pull/86368