[llvm] [Target][RISCV] Add HwMode support to subregister index size/offset. (PR #86368)

[Craig Topper via llvm-commits]

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@@ -83,10 +83,24 @@ class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
   list<RegInfo> Objects = Ts;
 }
 
+class SubRegRange<int size, int offset = 0> {
+  int Size = size;      // Sub register size in bits.
+  int Offset = offset;  // Offset of the first bit of the sub-reg index.
+}
+
+class SubRegRangeByHwMode<list<HwMode> Ms = [], list<SubRegRange> Ts = []>
+    : HwModeSelect<Ms> {
+  // The length of this list must be the same as the length of Ms.
+  list<SubRegRange> Objects = Ts;
+}
+
 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
 class SubRegIndex<int size, int offset = 0> {
   string Namespace = "";
 
+  // The size/offset information, parameterized by a HW mode.
+  SubRegRangeByHwMode SubRegRanges;
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topperc wrote:

I copied the structure from how RegisterClass uses `RegInfos`. This is least disruptive for targets that don't care about HwMode.

https://github.com/llvm/llvm-project/pull/86368