[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads (PR #84965)

[Craig Topper via llvm-commits]

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@@ -220,7 +220,8 @@ struct TypePairAndMemDesc {
            Align >= Other.Align &&
            // FIXME: This perhaps should be stricter, but the current legality
            // rules are written only considering the size.
-           MemTy.getSizeInBits() == Other.MemTy.getSizeInBits();
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topperc wrote:

I guess since `isCompatible` just checks the size, I guess `{v16s8, p0, s128, 8}` or `{v16s8, p0, v16s8, 8}` are equivalent for AArch64?

So using `{nxv1s8, p0, nxv1s8, 8}` would be correct for RISC-V.

https://github.com/llvm/llvm-project/pull/84965