[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads (PR #84965)

[Craig Topper via llvm-commits]

================
@@ -220,7 +220,8 @@ struct TypePairAndMemDesc {
            Align >= Other.Align &&
            // FIXME: This perhaps should be stricter, but the current legality
            // rules are written only considering the size.
-           MemTy.getSizeInBits() == Other.MemTy.getSizeInBits();
----------------
topperc wrote:

The third parameter definitely needs to be a scalable type to match true size of nxv1s8.

AArch64 has this for vectors, but they don't support scalable vectors yet. The third parameter is a scalar the same total size as the vector
```
      .legalForTypesWithMemDesc({{s8, p0, s8, 8},                                
                                 {s16, p0, s16, 8},                              
                                 {s32, p0, s32, 8},                              
                                 {s64, p0, s64, 8},                              
                                 {p0, p0, s64, 8},                               
                                 {s128, p0, s128, 8},                            
                                 {v8s8, p0, s64, 8},                             
                                 {v16s8, p0, s128, 8},                           
                                 {v4s16, p0, s64, 8},                            
                                 {v8s16, p0, s128, 8},                           
                                 {v2s32, p0, s64, 8},                            
                                 {v4s32, p0, s128, 8},                           
                                 {v2s64, p0, s128, 8}})   
```

So `{nxv1s8, p0, s8, 8}` seems wrong to me, but I'm not sure what we can put there.

https://github.com/llvm/llvm-project/pull/84965