[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michal Terepeta via llvm-commits]

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@@ -307,44 +307,44 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>, Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
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michalt wrote:

That's a good question! I think the tricky part is that the semantics and latencies of VCIX instructions are only defined for a specific implementation of a coprocessor, which makes it difficult to come up with any particular grouping for them (despite the names, the semantics of the VCIX instructions completely depends on a particular coprocessor). One person could attach coprocessor A to an X280 and someone else could attach a coprocessor B with widely different scheduling needs. And if they wanted to define the precise scheduling information for their respective coprocessors, they'd probably need this fine-grained control, right? At least that's how I understand this. But let me know if I'm missing or misunderstanding something. 🙂

https://github.com/llvm/llvm-project/pull/86093