[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michal Terepeta via llvm-commits]

================
@@ -944,6 +944,52 @@ let Latency = 3 in
 
 def : InstRW<[WriteIALU], (instrs COPY)>;
 
+// VCIX
+//
+// In principle we don't know the latency of any VCIX instructions. But instead
+// of taking the default of 1, which can lead to issues [1], we assume that they
+// have a fairly high latency.
+//
+// [1] https://github.com/llvm/llvm-project/issues/83391
+foreach mx = SchedMxList in {
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+  defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
+  let Latency = 20, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
----------------
michalt wrote:

That's a good idea! How about doing something like `Latency = !mul(Cycles, 10)`? (where `Cycles = SiFive7GetCyclesDefault<mx>.c`)

https://github.com/llvm/llvm-project/pull/86093