[llvm] [RISCV] Combine (mul (zext, zext)) -> (zext (mul (zext, zext))) (PR #86465)

[Luke Lau via llvm-commits]

lukel97 wrote:

Just did some testing on llvm-test-suite, this actually breaks some vwmacc patterns we don't have in our in-tree tests. Because we go from:

```
        t8: nxv1i64 = zero_extend t2
        t9: nxv1i64 = zero_extend t4
      t11: nxv1i64 = mul t8, t9
      t10: nxv1i64 = zero_extend t6
    t12: nxv1i64 = add t11, t10
```

```
          t21: nxv1i16 = zero_extend t2
          t22: nxv1i16 = zero_extend t4
        t23: nxv1i16 = mul t21, t22
      t25: nxv1i64 = zero_extend t23
      t10: nxv1i64 = zero_extend t6
    t12: nxv1i64 = add t25, t10
```

Will take a look to see if we can preserve it

https://github.com/llvm/llvm-project/pull/86465