[llvm] [SelectionDAG] Use computeForAddSub to prove that ISD::ADD is not 0 (PR #86453)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: AtariDreams (AtariDreams)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/86453.diff


1 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+8-1) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0ab5142ab81676..8e79ab9541676b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5405,7 +5405,14 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
       if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
           isKnownNeverZero(Op.getOperand(0), Depth + 1))
         return true;
-    // TODO: There are a lot more cases we can prove for add.
+    if (KnownBits::computeForAddSub(
+            true, Op->getFlags().hasNoSignedWrap(),
+            Op->getFlags().hasNoUnsignedWrap(),
+            computeKnownBits(Op.getOperand(0), Depth + 1),
+            computeKnownBits(Op.getOperand(1), Depth + 1))
+            .isNonZero())
+      return true;
+    // TODO: Are there more cases we can prove for add not covered by the above?
     break;
 
   case ISD::SUB: {

``````````

</details>


https://github.com/llvm/llvm-project/pull/86453