[llvm] [SelectionDAG] Use computeForAddSub to prove that ISD::ADD is not 0 (PR #86453)

[via llvm-commits]

https://github.com/AtariDreams created https://github.com/llvm/llvm-project/pull/86453

None

>From 0225f3c35afd92fed2c4f443a4cc46e9de67a8e4 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sun, 24 Mar 2024 16:30:57 -0400
Subject: [PATCH] [SelectionDAG] Use computeForAddSub to prove that ISD::ADD is
 not 0

---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0ab5142ab81676..8e79ab9541676b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5405,7 +5405,14 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
       if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
           isKnownNeverZero(Op.getOperand(0), Depth + 1))
         return true;
-    // TODO: There are a lot more cases we can prove for add.
+    if (KnownBits::computeForAddSub(
+            true, Op->getFlags().hasNoSignedWrap(),
+            Op->getFlags().hasNoUnsignedWrap(),
+            computeKnownBits(Op.getOperand(0), Depth + 1),
+            computeKnownBits(Op.getOperand(1), Depth + 1))
+            .isNonZero())
+      return true;
+    // TODO: Are there more cases we can prove for add not covered by the above?
     break;
 
   case ISD::SUB: {