[llvm] [Target][RISCV] Add HwMode support to subregister index size/offset. (PR #86368)

[Craig Topper via llvm-commits]

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@@ -64,9 +64,14 @@ def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
 def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
 
 // GPR sizes change with HwMode.
-// FIXME: Support HwMode in SubRegIndex?
-def sub_gpr_even : SubRegIndex<-1>;
-def sub_gpr_odd  : SubRegIndex<-1, -1>;
+def sub_gpr_even : SubRegIndex<32> {
----------------
topperc wrote:

Isn't 32 consistent with the size we pass to the non-HwMode part of this?

```
class GPRRegisterClass<dag regList>                                              
    : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, regList> {              
  let RegInfos = XLenRI;                                                         
}    
```

https://github.com/llvm/llvm-project/pull/86368