[llvm] [Target][RISCV] Add HwMode support to subregister index size/offset. (PR #86368)

[Jessica Clarke via llvm-commits]

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@@ -90,16 +90,16 @@ def TestTarget : Target;
 // CHECK-LABEL: RegisterClass DRegs:
 
 // CHECK-LABEL: SubRegIndex ssub1:
-// CHECK:        Offset, Size: 16, 16
+// CHECK:        Offset, Size: { Default:16, 16 }
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jrtc27 wrote:

Perhaps this should use extra {} to group the pair? One could be forgiven for thinking the Default only applies to the first argument, and it'll look very strange once you add in more HwMode's.

https://github.com/llvm/llvm-project/pull/86368