[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> > One concern is that: I prefer to restrict vendors' scheduling infos to their own RISCVSchedXXX.td via mechanisms like InstRW, SchedVariant, etc.
> 
> I am in agreement with you with what I prefer.
> 
> What would be really nice is that each SchedModel does not have to say what is Unsupported and instead if it is not explicitly written in the model, then it is unsupported. We have the current case where every extension added to the compiler forces someone to specify that it is unsupported in every scheduler model.
> 
> WRT to `InstRW`, I am concerned that there could be situations where it gets out of hand having to name every instruction. I think this is harder to maintain compared to writing `UnsupportedXXX` in each model. For small number of instructions I am okay to look the other way.

I don't know if this situation will be true, models in AArch64 have heavy uses of `InstRW`. But I have an open mind on this.

> 
> I would be okay to let the approach taken in this PR through and have us explore how to fix this for unsupported extensions in general. WDYT @wangpc-pp?

Yeah, I'm OK with that.
Actually, I have put this `fixing unsupported extensions` issue in my TODO list for a long time. There will be a large number of breaks since this mechanism has existed for a very long long time. But I think we should try to fix it.

https://github.com/llvm/llvm-project/pull/86093