[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michael Maitland via llvm-commits]

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@@ -307,44 +307,44 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>, Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
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michaelmaitland wrote:

Do we need three separate SchedWrite's for each instruction. It looks like they all behave the same. For example:

```
defvar WriteVC_MX = !cast<SchedWrite>("WriteVC_" # m.MX);
  def "PseudoVC_" # NAME # "_SE_" # m.MX 
    : VPseudoVC_X<OpClass, RS1Class>, Sched<[WriteVC_MX]>;
  def "PseudoVC_V_" # NAME # "_SE_" # m.MX 
    : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>, Sched<[WriteVC_MX]>;
}
def "PseudoVC_V_" # NAME # "_" # m.MX 
  : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>, Sched<[WriteVC_MX]>;
```

If we would like to give a little more finer control than this suggestion, then are there any variants taht we can group together?

https://github.com/llvm/llvm-project/pull/86093