[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michael Maitland via llvm-commits]

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@@ -944,6 +944,52 @@ let Latency = 3 in
 
 def : InstRW<[WriteIALU], (instrs COPY)>;
 
+// VCIX
+//
+// In principle we don't know the latency of any VCIX instructions. But instead
+// of taking the default of 1, which can lead to issues [1], we assume that they
+// have a fairly high latency.
+//
+// [1] https://github.com/llvm/llvm-project/issues/83391
+foreach mx = SchedMxList in {
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+  defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
+  let Latency = 20, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
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michaelmaitland wrote:

I am interested to know why you picked 20 for the latency. Should the latency depend on LMUL (or Cycles)?

https://github.com/llvm/llvm-project/pull/86093