[llvm] [RISCV] Lower the alignment requirement for a GPR pair spill for Zdinx on RV32. (PR #85871)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> The test is long to make sure we generate enough spills to have a large offset. I'm open to suggestions on ways to shorten it.

Maybe a MIR test would be better? we can set frame info manually in MIR.

https://github.com/llvm/llvm-project/pull/85871