[llvm] [RISCV] Lower the alignment requirement for a GPR pair spill for Zdinx on RV32. (PR #85871)

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git-clang-format --diff 4bade55cc65db8b7f977dba4f13bf335e93317a8 3ea54632545daef748003814ee0aeef9a7376500 -- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 881aab955f..952dbf7a12 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -447,7 +447,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
       // Prefetch instructions require the offset to be 32 byte aligned.
       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
     } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
-                 Opc == RISCV::PseudoRV32ZdinxSD) &&
+                Opc == RISCV::PseudoRV32ZdinxSD) &&
                Lo12 >= 2044) {
       // This instruction will be split into 2 instructions. The second
       // instruction will add 4 to the immediate. If that would overflow 12

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https://github.com/llvm/llvm-project/pull/85871