[llvm] [AArch64] Remove copy in SVE/SME predicate spill and fill (PR #81716)

[Sander de Smalen via llvm-commits]

================
@@ -1770,6 +1788,15 @@ class AArch64Operand : public MCParsedAsmOperand {
     Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
   }
 
+  void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    unsigned Reg = getReg();
+    // Normalise to PPR
+    if (Reg >= AArch64::PN0)
----------------
sdesmalen-arm wrote:

nit:
```suggestion
    if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15)
```

https://github.com/llvm/llvm-project/pull/81716