[llvm] [BOLT] Refactor instruction creation interface. NFCI (PR #85292)
Maksim Panchenko via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 14 11:23:53 PDT 2024
https://github.com/maksfb created https://github.com/llvm/llvm-project/pull/85292
Refactor MCPlusBuilder's create{Instruction}() functions that used to return bool. We almost never check the return value as we rely on llvm_unreachable() to detect unimplemented functionality. There were a couple of cases that checked the return value, but they would hit the unreachable condition first (at least in debug builds) before the return value gets checked.
>From 4001589f1c0e6155e3815c3507ac55d9d7029a4d Mon Sep 17 00:00:00 2001
From: Maksim Panchenko <maks at fb.com>
Date: Wed, 13 Mar 2024 21:46:27 -0700
Subject: [PATCH] [BOLT] Refactor instruction creation interface. NFCI
Refactor MCPlusBuilder's create{Instruction}() functions that used to
return bool. We almost never check the return value as we rely on
llvm_unreachable() to detect unimplemented functionality. There were a
couple of cases that checked the return value, but they would hit the
unreachable condition first (at least in debug builds) before the
return value gets checked.
---
bolt/include/bolt/Core/MCPlusBuilder.h | 52 +++++-------------
bolt/lib/Passes/BinaryPasses.cpp | 7 ++-
bolt/lib/Passes/ShrinkWrapping.cpp | 44 ++++++---------
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 23 +++-----
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp | 13 ++---
bolt/lib/Target/X86/X86MCPlusBuilder.cpp | 54 ++++++++-----------
bolt/unittests/Core/MCPlusBuilder.cpp | 10 ++--
7 files changed, 70 insertions(+), 133 deletions(-)
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h
index 6bb76d1b917db3..9220414b2e9501 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -487,10 +487,9 @@ class MCPlusBuilder {
llvm_unreachable("not implemented");
}
- virtual bool createDirectCall(MCInst &Inst, const MCSymbol *Target,
+ virtual void createDirectCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx, bool IsTailCall) {
llvm_unreachable("not implemented");
- return false;
}
virtual MCPhysReg getX86R11() const { llvm_unreachable("not implemented"); }
@@ -1534,15 +1533,13 @@ class MCPlusBuilder {
}
/// Create a no-op instruction.
- virtual bool createNoop(MCInst &Inst) const {
+ virtual void createNoop(MCInst &Inst) const {
llvm_unreachable("not implemented");
- return false;
}
/// Create a return instruction.
- virtual bool createReturn(MCInst &Inst) const {
+ virtual void createReturn(MCInst &Inst) const {
llvm_unreachable("not implemented");
- return false;
}
/// Store \p Target absolute address to \p RegName
@@ -1556,32 +1553,23 @@ class MCPlusBuilder {
/// Creates a new unconditional branch instruction in Inst and set its operand
/// to TBB.
- ///
- /// Returns true on success.
- virtual bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
+ virtual void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
- return false;
}
/// Creates a new call instruction in Inst and sets its operand to
/// Target.
- ///
- /// Returns true on success.
- virtual bool createCall(MCInst &Inst, const MCSymbol *Target,
+ virtual void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) {
llvm_unreachable("not implemented");
- return false;
}
/// Creates a new tail call instruction in Inst and sets its operand to
/// Target.
- ///
- /// Returns true on success.
- virtual bool createTailCall(MCInst &Inst, const MCSymbol *Target,
+ virtual void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) {
llvm_unreachable("not implemented");
- return false;
}
virtual void createLongTailCall(InstructionListType &Seq,
@@ -1590,43 +1578,36 @@ class MCPlusBuilder {
}
/// Creates a trap instruction in Inst.
- ///
- /// Returns true on success.
- virtual bool createTrap(MCInst &Inst) const {
+ virtual void createTrap(MCInst &Inst) const {
llvm_unreachable("not implemented");
- return false;
}
/// Creates an instruction to bump the stack pointer just like a call.
- virtual bool createStackPointerIncrement(MCInst &Inst, int Size = 8,
+ virtual void createStackPointerIncrement(MCInst &Inst, int Size = 8,
bool NoFlagsClobber = false) const {
llvm_unreachable("not implemented");
- return false;
}
/// Creates an instruction to move the stack pointer just like a ret.
- virtual bool createStackPointerDecrement(MCInst &Inst, int Size = 8,
+ virtual void createStackPointerDecrement(MCInst &Inst, int Size = 8,
bool NoFlagsClobber = false) const {
llvm_unreachable("not implemented");
- return false;
}
/// Create a store instruction using \p StackReg as the base register
/// and \p Offset as the displacement.
- virtual bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg,
+ virtual void createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg,
int Offset, const MCPhysReg &SrcReg,
int Size) const {
llvm_unreachable("not implemented");
- return false;
}
- virtual bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
+ virtual void createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
const MCPhysReg &IndexReg, int64_t Offset,
const MCExpr *OffsetExpr,
const MCPhysReg &AddrSegmentReg,
const MCPhysReg &DstReg, int Size) const {
llvm_unreachable("not implemented");
- return false;
}
virtual InstructionListType createLoadImmediate(const MCPhysReg Dest,
@@ -1636,32 +1617,27 @@ class MCPlusBuilder {
/// Create a fragment of code (sequence of instructions) that load a 32-bit
/// address from memory, zero-extends it to 64 and jump to it (indirect jump).
- virtual bool
+ virtual void
createIJmp32Frag(SmallVectorImpl<MCInst> &Insts, const MCOperand &BaseReg,
const MCOperand &Scale, const MCOperand &IndexReg,
const MCOperand &Offset, const MCOperand &TmpReg) const {
llvm_unreachable("not implemented");
- return false;
}
/// Create a load instruction using \p StackReg as the base register
/// and \p Offset as the displacement.
- virtual bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
+ virtual void createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
int Offset, const MCPhysReg &DstReg,
int Size) const {
llvm_unreachable("not implemented");
- return false;
}
/// Creates a call frame pseudo instruction. A single operand identifies which
/// MCCFIInstruction this MCInst is referring to.
- ///
- /// Returns true on success.
- virtual bool createCFI(MCInst &Inst, int64_t Offset) const {
+ virtual void createCFI(MCInst &Inst, int64_t Offset) const {
Inst.clear();
Inst.setOpcode(TargetOpcode::CFI_INSTRUCTION);
Inst.addOperand(MCOperand::createImm(Offset));
- return true;
}
/// Create an inline version of memcpy(dest, src, 1).
diff --git a/bolt/lib/Passes/BinaryPasses.cpp b/bolt/lib/Passes/BinaryPasses.cpp
index d2850b03e2e13f..bf1c2ddd37dd24 100644
--- a/bolt/lib/Passes/BinaryPasses.cpp
+++ b/bolt/lib/Passes/BinaryPasses.cpp
@@ -1056,10 +1056,9 @@ void Peepholes::addTailcallTraps(BinaryFunction &Function) {
MCInst *Inst = BB.getLastNonPseudoInstr();
if (Inst && MIB->isTailCall(*Inst) && MIB->isIndirectBranch(*Inst)) {
MCInst Trap;
- if (MIB->createTrap(Trap)) {
- BB.addInstruction(Trap);
- ++TailCallTraps;
- }
+ MIB->createTrap(Trap);
+ BB.addInstruction(Trap);
+ ++TailCallTraps;
}
}
}
diff --git a/bolt/lib/Passes/ShrinkWrapping.cpp b/bolt/lib/Passes/ShrinkWrapping.cpp
index 9a1f9d72623a38..c9706500758d1f 100644
--- a/bolt/lib/Passes/ShrinkWrapping.cpp
+++ b/bolt/lib/Passes/ShrinkWrapping.cpp
@@ -680,16 +680,15 @@ void StackLayoutModifier::performChanges() {
if (StackPtrReg != BC.MIB->getFramePointer())
Adjustment = -Adjustment;
if (IsLoad)
- Success = BC.MIB->createRestoreFromStack(
- Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size);
+ BC.MIB->createRestoreFromStack(Inst, StackPtrReg,
+ StackOffset + Adjustment, Reg, Size);
else if (IsStore)
- Success = BC.MIB->createSaveToStack(
- Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size);
+ BC.MIB->createSaveToStack(Inst, StackPtrReg, StackOffset + Adjustment,
+ Reg, Size);
LLVM_DEBUG({
dbgs() << "Adjusted instruction: ";
Inst.dump();
});
- assert(Success);
}
}
}
@@ -1653,19 +1652,13 @@ Expected<MCInst> ShrinkWrapping::createStackAccess(int SPVal, int FPVal,
if (SPVal != StackPointerTracking::SUPERPOSITION &&
SPVal != StackPointerTracking::EMPTY) {
if (FIE.IsLoad) {
- if (!BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getStackPointer(),
- FIE.StackOffset - SPVal, FIE.RegOrImm,
- FIE.Size)) {
- return createFatalBOLTError(
- "createRestoreFromStack: not supported on this platform\n");
- }
- } else {
- if (!BC.MIB->createSaveToStack(NewInst, BC.MIB->getStackPointer(),
+ BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getStackPointer(),
FIE.StackOffset - SPVal, FIE.RegOrImm,
- FIE.Size)) {
- return createFatalBOLTError(
- "createSaveToStack: not supported on this platform\n");
- }
+ FIE.Size);
+ } else {
+ BC.MIB->createSaveToStack(NewInst, BC.MIB->getStackPointer(),
+ FIE.StackOffset - SPVal, FIE.RegOrImm,
+ FIE.Size);
}
if (CreatePushOrPop)
BC.MIB->changeToPushOrPop(NewInst);
@@ -1675,19 +1668,12 @@ Expected<MCInst> ShrinkWrapping::createStackAccess(int SPVal, int FPVal,
FPVal != StackPointerTracking::EMPTY);
if (FIE.IsLoad) {
- if (!BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getFramePointer(),
- FIE.StackOffset - FPVal, FIE.RegOrImm,
- FIE.Size)) {
- return createFatalBOLTError(
- "createRestoreFromStack: not supported on this platform\n");
- }
- } else {
- if (!BC.MIB->createSaveToStack(NewInst, BC.MIB->getFramePointer(),
+ BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getFramePointer(),
FIE.StackOffset - FPVal, FIE.RegOrImm,
- FIE.Size)) {
- return createFatalBOLTError(
- "createSaveToStack: not supported on this platform\n");
- }
+ FIE.Size);
+ } else {
+ BC.MIB->createSaveToStack(NewInst, BC.MIB->getFramePointer(),
+ FIE.StackOffset - FPVal, FIE.RegOrImm, FIE.Size);
}
return NewInst;
}
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index ec00602ac60b5f..0ae9d3668b93bb 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -1026,7 +1026,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return Code;
}
- bool createTailCall(MCInst &Inst, const MCSymbol *Target,
+ void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true);
}
@@ -1036,11 +1036,10 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
createShortJmp(Seq, Target, Ctx, /*IsTailCall*/ true);
}
- bool createTrap(MCInst &Inst) const override {
+ void createTrap(MCInst &Inst) const override {
Inst.clear();
Inst.setOpcode(AArch64::BRK);
Inst.addOperand(MCOperand::createImm(1));
- return true;
}
bool convertJmpToTailCall(MCInst &Inst) override {
@@ -1068,16 +1067,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
Inst.getOperand(0).getImm() == 0;
}
- bool createNoop(MCInst &Inst) const override {
+ void createNoop(MCInst &Inst) const override {
Inst.setOpcode(AArch64::HINT);
Inst.clear();
Inst.addOperand(MCOperand::createImm(0));
- return true;
}
bool mayStore(const MCInst &Inst) const override { return false; }
- bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
+ void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
bool IsTailCall) override {
Inst.setOpcode(IsTailCall ? AArch64::B : AArch64::BL);
Inst.clear();
@@ -1086,7 +1084,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
*Ctx, 0)));
if (IsTailCall)
convertJmpToTailCall(Inst);
- return true;
}
bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
@@ -1293,14 +1290,13 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return true;
}
- bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
+ void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
Inst.setOpcode(AArch64::B);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx),
*Ctx, 0)));
- return true;
}
bool shouldRecordCodeRelocation(uint64_t RelType) const override {
@@ -1353,14 +1349,13 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return StringRef("\0\0\0\0", 4);
}
- bool createReturn(MCInst &Inst) const override {
+ void createReturn(MCInst &Inst) const override {
Inst.setOpcode(AArch64::RET);
Inst.clear();
Inst.addOperand(MCOperand::createReg(AArch64::LR));
- return true;
}
- bool createStackPointerIncrement(
+ void createStackPointerIncrement(
MCInst &Inst, int Size,
bool NoFlagsClobber = false /*unused for AArch64*/) const override {
Inst.setOpcode(AArch64::SUBXri);
@@ -1369,10 +1364,9 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createReg(AArch64::SP));
Inst.addOperand(MCOperand::createImm(Size));
Inst.addOperand(MCOperand::createImm(0));
- return true;
}
- bool createStackPointerDecrement(
+ void createStackPointerDecrement(
MCInst &Inst, int Size,
bool NoFlagsClobber = false /*unused for AArch64*/) const override {
Inst.setOpcode(AArch64::ADDXri);
@@ -1381,7 +1375,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createReg(AArch64::SP));
Inst.addOperand(MCOperand::createImm(Size));
Inst.addOperand(MCOperand::createImm(0));
- return true;
}
void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg,
diff --git a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
index e19c070b081733..ab9623d5c51b28 100644
--- a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+++ b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
@@ -219,46 +219,43 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
return true;
}
- bool createReturn(MCInst &Inst) const override {
+ void createReturn(MCInst &Inst) const override {
// TODO "c.jr ra" when RVC is enabled
Inst.setOpcode(RISCV::JALR);
Inst.clear();
Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(MCOperand::createReg(RISCV::X1));
Inst.addOperand(MCOperand::createImm(0));
- return true;
}
- bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
+ void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
Inst.setOpcode(RISCV::JAL);
Inst.clear();
Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
- return true;
}
StringRef getTrapFillValue() const override {
return StringRef("\0\0\0\0", 4);
}
- bool createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
+ void createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) {
Inst.setOpcode(Opcode);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(RISCVMCExpr::create(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx),
RISCVMCExpr::VK_RISCV_CALL, *Ctx)));
- return true;
}
- bool createCall(MCInst &Inst, const MCSymbol *Target,
+ void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createCall(RISCV::PseudoCALL, Inst, Target, Ctx);
}
- bool createTailCall(MCInst &Inst, const MCSymbol *Target,
+ void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createCall(RISCV::PseudoTAIL, Inst, Target, Ctx);
}
diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
index 79935a9f5b34de..273296f45aba73 100644
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -2230,7 +2230,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
return true;
}
- bool createStackPointerIncrement(MCInst &Inst, int Size,
+ void createStackPointerIncrement(MCInst &Inst, int Size,
bool NoFlagsClobber) const override {
if (NoFlagsClobber) {
Inst.setOpcode(X86::LEA64r);
@@ -2241,17 +2241,16 @@ class X86MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.addOperand(MCOperand::createImm(-Size)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
- return true;
+ return;
}
Inst.setOpcode(X86::SUB64ri8);
Inst.clear();
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createImm(Size));
- return true;
}
- bool createStackPointerDecrement(MCInst &Inst, int Size,
+ void createStackPointerDecrement(MCInst &Inst, int Size,
bool NoFlagsClobber) const override {
if (NoFlagsClobber) {
Inst.setOpcode(X86::LEA64r);
@@ -2262,22 +2261,22 @@ class X86MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.addOperand(MCOperand::createImm(Size)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
- return true;
+ return;
}
Inst.setOpcode(X86::ADD64ri8);
Inst.clear();
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createImm(Size));
- return true;
}
- bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset,
+ void createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset,
const MCPhysReg &SrcReg, int Size) const override {
unsigned NewOpcode;
switch (Size) {
default:
- return false;
+ llvm_unreachable("Invalid operand size");
+ return;
case 2: NewOpcode = X86::MOV16mr; break;
case 4: NewOpcode = X86::MOV32mr; break;
case 8: NewOpcode = X86::MOV64mr; break;
@@ -2290,10 +2289,9 @@ class X86MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createImm(Offset)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
Inst.addOperand(MCOperand::createReg(SrcReg));
- return true;
}
- bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
+ void createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
int Offset, const MCPhysReg &DstReg,
int Size) const override {
return createLoad(Inst, StackReg, /*Scale=*/1, /*IndexReg=*/X86::NoRegister,
@@ -2301,14 +2299,15 @@ class X86MCPlusBuilder : public MCPlusBuilder {
DstReg, Size);
}
- bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
+ void createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
const MCPhysReg &IndexReg, int64_t Offset,
const MCExpr *OffsetExpr, const MCPhysReg &AddrSegmentReg,
const MCPhysReg &DstReg, int Size) const override {
unsigned NewOpcode;
switch (Size) {
default:
- return false;
+ llvm_unreachable("Invalid operand size");
+ return;
case 2: NewOpcode = X86::MOV16rm; break;
case 4: NewOpcode = X86::MOV32rm; break;
case 8: NewOpcode = X86::MOV64rm; break;
@@ -2324,7 +2323,6 @@ class X86MCPlusBuilder : public MCPlusBuilder {
else
Inst.addOperand(MCOperand::createImm(Offset)); // Displacement
Inst.addOperand(MCOperand::createReg(AddrSegmentReg)); // AddrSegmentReg
- return true;
}
InstructionListType createLoadImmediate(const MCPhysReg Dest,
@@ -2338,7 +2336,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
return Insts;
}
- bool createIJmp32Frag(SmallVectorImpl<MCInst> &Insts,
+ void createIJmp32Frag(SmallVectorImpl<MCInst> &Insts,
const MCOperand &BaseReg, const MCOperand &Scale,
const MCOperand &IndexReg, const MCOperand &Offset,
const MCOperand &TmpReg) const override {
@@ -2362,19 +2360,16 @@ class X86MCPlusBuilder : public MCPlusBuilder {
Insts.push_back(Load);
Insts.push_back(IJmp);
- return true;
}
- bool createNoop(MCInst &Inst) const override {
+ void createNoop(MCInst &Inst) const override {
Inst.setOpcode(X86::NOOP);
Inst.clear();
- return true;
}
- bool createReturn(MCInst &Inst) const override {
+ void createReturn(MCInst &Inst) const override {
Inst.setOpcode(X86::RET64);
Inst.clear();
- return true;
}
InstructionListType createInlineMemcpy(bool ReturnEnd) const override {
@@ -2731,25 +2726,23 @@ class X86MCPlusBuilder : public MCPlusBuilder {
return FoundOne;
}
- bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
+ void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
Inst.setOpcode(X86::JMP_1);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
- return true;
}
- bool createCall(MCInst &Inst, const MCSymbol *Target,
+ void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
Inst.setOpcode(X86::CALL64pcrel32);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx)));
- return true;
}
- bool createTailCall(MCInst &Inst, const MCSymbol *Target,
+ void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true);
}
@@ -2761,10 +2754,9 @@ class X86MCPlusBuilder : public MCPlusBuilder {
createDirectCall(Seq.back(), Target, Ctx, /*IsTailCall*/ true);
}
- bool createTrap(MCInst &Inst) const override {
+ void createTrap(MCInst &Inst) const override {
Inst.clear();
Inst.setOpcode(X86::TRAP);
- return true;
}
bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
@@ -2866,7 +2858,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
Inst.setOpcode(X86::LFENCE);
}
- bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
+ void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
bool IsTailCall) override {
Inst.clear();
Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32);
@@ -2874,7 +2866,6 @@ class X86MCPlusBuilder : public MCPlusBuilder {
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx)));
if (IsTailCall)
setTailCall(Inst);
- return true;
}
void createShortJmp(InstructionListType &Seq, const MCSymbol *Target,
@@ -3546,7 +3537,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
}
private:
- bool createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
+ void createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
MCContext *Ctx) const {
Inst.setOpcode(X86::MOV64rm);
Inst.clear();
@@ -3558,11 +3549,9 @@ class X86MCPlusBuilder : public MCPlusBuilder {
MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None,
*Ctx))); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
-
- return true;
}
- bool createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
+ void createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
MCContext *Ctx) const {
Inst.setOpcode(X86::LEA64r);
Inst.clear();
@@ -3574,7 +3563,6 @@ class X86MCPlusBuilder : public MCPlusBuilder {
MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None,
*Ctx))); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
- return true;
}
};
diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp
index 63448039c53e67..daf9f392b82281 100644
--- a/bolt/unittests/Core/MCPlusBuilder.cpp
+++ b/bolt/unittests/Core/MCPlusBuilder.cpp
@@ -134,9 +134,8 @@ TEST_P(MCPlusBuilderTester, ReplaceRegWithImm) {
TEST_P(MCPlusBuilderTester, Annotation) {
MCInst Inst;
- bool Success = BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
- BC->Ctx.get());
- ASSERT_TRUE(Success);
+ BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
+ BC->Ctx.get());
MCSymbol *LPSymbol = BC->Ctx->createNamedTempSymbol("LP");
uint64_t Value = INT32_MIN;
// Test encodeAnnotationImm using this indirect way
@@ -151,9 +150,8 @@ TEST_P(MCPlusBuilderTester, Annotation) {
// Large int64 should trigger an out of range assertion
Value = 0x1FF'FFFF'FFFF'FFFFULL;
Inst.clear();
- Success = BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
- BC->Ctx.get());
- ASSERT_TRUE(Success);
+ BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
+ BC->Ctx.get());
ASSERT_DEATH(BC->MIB->addEHInfo(Inst, MCPlus::MCLandingPad(LPSymbol, Value)),
"annotation value out of range");
}
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