[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)
Alfie Richards via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 14 04:17:14 PDT 2024
================
@@ -1347,6 +1368,14 @@ class ARMOperand : public MCParsedAsmOperand {
bool isRegListWithAPSR() const {
return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
}
+ bool isDReg() const {
+ return isReg() &&
+ ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg.RegNum);
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AlfieRichardsArm wrote:
Whoops, thank you! I am surprised this didn't catch any tests.
https://github.com/llvm/llvm-project/pull/83436
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