[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Ivan Kosarev via llvm-commits]

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@@ -1564,6 +1562,10 @@ class AsmParser {
   // method shall be called for all operands as opposed to only those
   // that have their own specified custom parsers.
   bit CallCustomParserForAllOperands = false;
+
+  // PreferSmallerInstructions - Should the assembly matcher prefer the smaller
+  // instructions.
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kosarev wrote:

Regarding (b), I think ideally we would want ambiguous matchables to be caught and reported (which is currently impossible to do because we don't have information about mutually exclusive assembler predicates and probably because of other reasons as well -- note that the code that is supposed to catch ambiguities is effectively disabled) rather than to be ordered in any particular way (which is unfortunately how it works currently and unfortunately part of that mechanics relies on comparing names).

So the opposite of preferring smaller instructions is not establishing any ordering based on the size of instructions, I would expect.

https://github.com/llvm/llvm-project/pull/83436