[llvm] [AArch64] Support scalable offsets with isLegalAddressingMode (PR #83255)

[David Green via llvm-commits]

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@@ -16374,15 +16374,31 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
 
   if (Ty->isScalableTy()) {
     if (isa<ScalableVectorType>(Ty)) {
+      // See if we have a foldable vscale-based offset, for vector types which
+      // are either legal or smaller than the minimum; more work will be
+      // required if we need to consider addressing for types which need
+      // legalization by splitting.
+      uint64_t VecNumBytes = DL.getTypeSizeInBits(Ty).getKnownMinValue() / 8;
+      if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale &&
+          (AM.ScalableOffset % VecNumBytes == 0) && VecNumBytes <= 16 &&
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davemgreen wrote:

I've been staring at this. Is it worth checking the size is one that we expect, or does that not come up or get legalized to another type?

For larger than legal types (that are split into 2) I believe they should be legalized to two address modes, the second with Idx+1. It may be best leaving that for the future though, it is up to you.

https://github.com/llvm/llvm-project/pull/83255