[llvm] [AArch64] Support scalable offsets with isLegalAddressingMode (PR #83255)

[David Green via llvm-commits]

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@@ -16374,15 +16374,31 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
 
   if (Ty->isScalableTy()) {
     if (isa<ScalableVectorType>(Ty)) {
+      // See if we have a foldable vscale-based offset, for vector types which
+      // are either legal or smaller than the minimum; more work will be
+      // required if we need to consider addressing for types which need
+      // legalization by splitting.
+      uint64_t VecNumBytes = DL.getTypeSizeInBits(Ty).getKnownMinValue() / 8;
+      if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale &&
+          (AM.ScalableOffset % VecNumBytes == 0) && VecNumBytes <= 16 &&
+          isPowerOf2_64(VecNumBytes)) {
+        int64_t Idx = AM.ScalableOffset / (int64_t)VecNumBytes;
+        return Idx >= -8 && Idx <= 7;
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davemgreen wrote:

I think `isInt<4>(Idx)`, but may have the number of bits off.

https://github.com/llvm/llvm-project/pull/83255