[llvm] [AArch64][GlobalISel] Legalize Insert vector element (PR #81453)

[David Green via llvm-commits]

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@@ -883,9 +883,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampMaxNumElements(1, p0, 2);
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
-      .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
+      .legalIf(
+          typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
       .moreElementsToNextPow2(0)
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davemgreen wrote:

I don't really agree that we need float types for this. `{v8i16, i16, i64}` is just as legal as `{v8f16, f16, i64}` is, providing the i16 comes from a fpr register bank. We have seen many cases where we could be more optimally keeping values in fp types in SDAG, but doesn't due to the legalization forcing the types of integer values.

fp types are needed to get bf16 working.

https://github.com/llvm/llvm-project/pull/81453