[llvm] [AArch64][GlobalISel] Legalize Insert vector element (PR #81453)

[David Green via llvm-commits]

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@@ -407,6 +411,14 @@ void AArch64RegisterBankInfo::applyMappingImpl(
             OpdMapper.getInstrMapping().getID() <= 4) &&
            "Don't know how to handle that ID");
     return applyDefaultMapping(OpdMapper);
+  case TargetOpcode::G_INSERT_VECTOR_ELT: {
+    // Extend smaller gpr operands to 32 bit.
+    Builder.setInsertPt(*MI.getParent(), MI.getIterator());
+    auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg());
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davemgreen wrote:

It only has s8/s16 types at the moment, not integer/fp types, and they can be equally legal after selection. At least that is how it currently works for AArch64 and it seems it can work fine.

https://github.com/llvm/llvm-project/pull/81453